- Aug 06, 2024
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Tom Rini authored
Signed-off-by:Tom Rini <trini@konsulko.com>
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- Aug 05, 2024
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Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by: -
Tom Rini authored
Simon Glass <sjg@chromium.org> says: This series includes fixes to get some rockchip and nvidia boards working again. It also drops the broken Beaglebone Black config and provides a devicetree fix for coral (x86).
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The code here is confusing due to large blocks which are #ifdefed out. Add a function phase_sdram_init() which returns whether SDRAM init should happen in the current phase, using that as needed to control the code flow. This increases code size by about 500 bytes in SPL when the cache is on, since it must call the rather large rockchip_sdram_size() function. Signed-off-by:Simon Glass <sjg@chromium.org>
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At present gd->ram_size is 0 in SPL, meaning that it is not possible to enable the cache. Correct this by always populating the RAM size correctly. This increases code size by about 500 bytes in SPL, since it must call the rather large rockchip_sdram_size() function. Signed-off-by:
Quentin Schulz <quentin.schulz@cherry.de>
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On some boards, the bloblist is created in SPL once SDRAM is ready. It cannot be accessed until that point, so is not available early in SPL. Add a condition to avoid a hang in this case. This fixes a hang in chromebook_coral Fixes: 70fe2385 ("fdt: Allow the devicetree to come from a bloblist") Signed-off-by:
Raymond Mao <raymond.mao@linaro.org>
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There is no need to remove input files. It makes it harder to diagnose failures. Keep the payload file. There is no test for this condition, but one could be added. Signed-off-by:
Sughosh Ganu <sughosh.ganu@linaro.org>
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The tool must return an error code when invalid arguments are provided, otherwise binman has no way of knowing that anything went wrong. Correct this. Signed-off-by:
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Tools cannot be assumed to be present. Add a check for this with the mkeficpasule tool. Signed-off-by:
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Now that this tool has a version number, collect it. Signed-off-by: -
Tools should have an option to obtain the version, so add this to the mkeficapsule tool. Signed-off-by:
Ilias Apalodimas <ilias.apalodimas@linaro.org>
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- Aug 02, 2024
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https://gitlab.denx.de/u-boot/custodians/u-boot-imxTom Rini authored
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21846 - Convert warp7 to OF_UPSTREAM. - Add 'cpu' command to imx8m and imx93. - Enable CMD_ERASEENV for imx8mm/mp Phytec boards.
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Lukasz Majewski authored
This change adds support for PCIe connected nvme disk - phyBOARD-Polis base board. One needs to call following commands in u-boot: > pci enum > nvme scan > nvme info And then ones to access proper file system (like fat[ls|load|write], ext4[ls|load|write]). Signed-off-by:Lukasz Majewski <lukma@denx.de>
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Hou Zhiqiang authored
Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by:Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Hou Zhiqiang authored
Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: -
Hou Zhiqiang authored
Added the original author Simon and myself. Signed-off-by:
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Hou Zhiqiang authored
Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus as a example. Signed-off-by:
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Hou Zhiqiang authored
Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C 1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C 2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C 3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C u-boot=> load mmc 1:2 c0000000 /hello_world.bin 66008 bytes read in 5 ms (12.6 MiB/s) u-boot=> dcache flush; icache flush u-boot=> cpu release 3 c0000000 Released CPU core (mpidr: 0x3) to address 0xc0000000 Signed-off-by: -
Hou Zhiqiang authored
Release the secondary cores through the PSCI request. Signed-off-by: -
Hou Zhiqiang authored
Add i.MX 8M Mini, Nano and Plus SoCs support. Signed-off-by: -
Hou Zhiqiang authored
Return CPU description string without newline character in the end. Signed-off-by: -
Hou Zhiqiang authored
Increase one more bit to cover all CPU types. Otherwise it shows wrong CPU info on some platforms, such as i.MX8M Plus: U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +0000) CPU: NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C Model: NXP i.MX8MPlus LPDDR4 EVK board Signed-off-by: -
Hou Zhiqiang authored
The cpu_freq stores the current CPU frequency in Hz. Signed-off-by:
Michael Trimarchi <michael@amarulasolutions.com>
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Hou Zhiqiang authored
Add test for API cpu_release_core(). Signed-off-by:
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Hou Zhiqiang authored
Add empty release CPU core function for testing. Signed-off-by:
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Hou Zhiqiang authored
Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by:
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Hou Zhiqiang authored
Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing for enabling the 'cpu' command, which depends on this to print CPU core frequency. Signed-off-by: -
Yannic Moog authored
Enable erasing environment with eraseenv command. Signed-off-by:Yannic Moog <y.moog@phytec.de>
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Yannic Moog authored
Enable erasing environment with eraseenv command. Signed-off-by: -
Yannic Moog authored
Enable erasing environment with eraseenv command. Signed-off-by: -
Fabio Estevam authored
Instead of using the local imx7s-warp devicetree copies from U-Boot, convert the imx7s-warp board to OF_UPSTREAM so that the upstream kernel devicetree can be used instead. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com>
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- Aug 01, 2024
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Print clk name in clk_enable and clk_disable. Make sense to know what clock get disabled/enabled before a system crash or system hang. Signed-off-by: -
The function returns the rate of the parent clock, the previous text made no sense at all. Fixes: 4aa78300 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by:
Alexander Dahl <ada@thorsis.com> Reviewed-by:
Sean Anderson <seanga2@gmail.com>
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Fix a logical inversion of the printed text. Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by:
Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by:
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Tom Rini authored
Christian Marangi <ansuelsmth@gmail.com> says: This series doesn't currently change anything and it does add all the additional OPs to make support of OF_UPSTREAM. While converting the mt7681/7686/7688/7623/7622 it was notice lots of discrepancy between the downstream dtsi and the upstream one and the clock ID between downstream clock ID and upstream clock ID. Upstream reference clock by names and clock are handled by the CCF (Common Clock Framework). The same can't be used here as we would quickly reach the max space allocated before relocation. The current mediatek clock driver reference all the parents and clocks with offset from the clk ID related to the different tables. Discrepancy between clock ID and the order in the clocks table cause one clock referenced for another or even crash for trying to access a clock at an offset that doesn't exist. To handle this and permit use of OF_UPSTREAM, various measure and changes are done to the mediatek clock driver to support it. This series have all the generic clock changes. Once this is merged, series for each SoC will came that will just change files in their dedicated clock driver. This is to prevent massive patch and to permit to split series, one for each SoC. As said at the start, these changes doesn't cause regression and are just expansion to the current API. Current behaviour is saved in every possible way (aside from the first 2 patch that fixes latent bugs)
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Add support for APMIXED parent in infra MUX. This is the case for mt7622 that reference APMIXED parents for the MUX1_SEL clock. We assume the second level parent is always APMIXED. Signed-off-by:Christian Marangi <ansuelsmth@gmail.com>
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Add support for GATEs for APMIXED OPs. It's possible that some APMIXED have also gates on top of PLL. This is the case for mt7622. Add support for this. Signed-off-by: -
Some simple MUX might require flags to specify the parent source. Implement MUX_FLAGS as a variant of the MUX macro that takes custom flags as last arg. Also implement MUX_MIXED_FLAGS for PARENT_MIXED implementation and MUX_MIXED with no additional flags. Signed-off-by: -
Upstream kernel linux might have a different clock ID order in their <soc>-clk.h header. This is the case of some clock ID for mt7623 that upstream use the shared header clk-mt7601.h This header doesn't have a well distincted order and have factor or mux in the middle of the CLK ID list. This is problematic with the mtk clock driver that expect everything well organized in block and apply offset to reference the clk in the different array. To solve this problem, implement in the mtk_clk_tree an additional option .id_offs_map, an array where each CLK ID can be remapped to what the driver expect permitting to reorganize the clock following the expected logic of fixed, factor, mux and gates. Each clock function is updated to tranparently handle this by first converting the clk ID to the remapped one. Signed-off-by: -
Provide common clk init function for infrasys that defaults to topckgen driver if clock-parent is not defined. This is the case for upstream DTSI that doesn't provide this entry. This is needed for infracfg driver that will make use of the unified gates + muxes implementation. Signed-off-by:
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