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Commit a45343a0 authored by Daniel Schwierzeck's avatar Daniel Schwierzeck
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dm: pci: add option to map virtual system memory base address


On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE
is still used as a virtual, CPU-mapped address instead of being used
as physical address. Converting all MIPS boards and generic MIPS code
to fix that is not trivial. Due to the approaching deadline for
PCI DM conversion, this workaround is required for MIPS boards with
PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved.

Add a compile-time option to let the PCI uclass core optionally map
the DRAM address to a physical address when adding the PCI region
of type PCI_REGION_SYS_MEMORY.

Signed-off-by: Daniel Schwierzeck's avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Reviewed-by: default avatarStefan Roese <sr@denx.de>
parent fe5ac459
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...@@ -54,6 +54,19 @@ config PCI_REGION_MULTI_ENTRY ...@@ -54,6 +54,19 @@ config PCI_REGION_MULTI_ENTRY
region type. This helps to add support for SoC's like OcteonTX/TX2 region type. This helps to add support for SoC's like OcteonTX/TX2
where every peripheral is on the PCI bus. where every peripheral is on the PCI bus.
config PCI_MAP_SYSTEM_MEMORY
bool "Map local system memory from a virtual base address"
depends on PCI || DM_PCI
depends on MIPS
default n
help
Say Y if base address of system memory is being used as a virtual address
instead of a physical address (e.g. on MIPS). The PCI core will then remap
the virtual memory base address to a physical address when adding the PCI
region of type PCI_REGION_SYS_MEMORY.
This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
being used as virtual address.
config PCI_SRIOV config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI" bool "Enable Single Root I/O Virtualization support for PCI"
depends on PCI || DM_PCI depends on PCI || DM_PCI
......
...@@ -1034,10 +1034,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, ...@@ -1034,10 +1034,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) { if (bd->bi_dram[i].size) {
phys_addr_t start = bd->bi_dram[i].start;
if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
pci_set_region(hose->regions + hose->region_count++, pci_set_region(hose->regions + hose->region_count++,
bd->bi_dram[i].start, start, start, bd->bi_dram[i].size,
bd->bi_dram[i].start,
bd->bi_dram[i].size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
} }
} }
......
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