- Jul 27, 2019
-
-
J721E allows for booting from primary or backup boot media. Both media can be chosen individually based on switch settings. ROM looks for a valid image in primary boot media, if not found then looks in backup boot media. In order to pass this boot media information to boot loader, ROM stores a value at a particular address. Add support for reading this information and determining the boot media correctly. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com>
-
The J721E SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable lower system costs of automotive applications such as infotainment, cluster, premium Audio, Gateway, industrial and a range of broad market applications. This SoC is designed around reducing the system cost by eliminating the need of an external system MCU and is targeted towards ASIL-B/C certification/requirements in addition to allowing complex software and system use-cases. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP, Two C66x floating point DSPs. * 3D GPU PowerVR Rogue 8XE GE8430 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and up to two DPI interfaces. * Integrated Ethernet switch supporting up to a total of 8 external ports in addition to legacy Ethernet switch of up to 2 ports. * System MMU (SMMU) Version 3.0 and advanced virtualisation capabilities. * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS * Centralized System Controller for Security, Power, and Resource Management (DMSC) See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: http://www.ti.com/lit/pdf/spruil1 Add base support for J721E SoC Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
-
k3_rproc driver is specifically meant for controlling an arm64 core using TISCI protocol. So rename the driver, Kconfig symbol, compatible and functions accordingly. While at it drop this remoteproc selection for a53 defconfig. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Update the k3_rproc driver to use the generic ti_sci_proc helper apis which simplifies the driver a bit. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Texas Instruments' K3 generation SoCs has specific modules/register spaces used for configuring the various aspects of a remote processor. These include power, reset, boot vector and other configuration features specific to each compute processor present on the SoC. These registers are managed by the System Controller such as DMSC on K3 AM65x SoCs. The Texas Instrument's System Control Interface (TI-SCI) Message Protocol is used to communicate to the System Controller from various compute processors to invoke specific services provided by the firmware running on the System Controller. Add a common processor control interface header file that can be used by multiple remoteproc drivers. The helper functions within this header file abstract the various TI SCI protocol ops for the remoteproc drivers, and allow them to request the System Controller to be able to program and manage various remote processors on the SoC. The common macros required by the R5 remoteproc driver were also added. The remoteproc drivers are expected to manage the life-cycle of their ti_sci_proc_dev local structures. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
-
'rproc list' is currently allowed only after probing all the available remoteproc devices. Given that 'rproc init' is updated to probe and initialize devices individually, allow the 'rproc list' command to print all probed devices at any point. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
'rproc init' does the probe and initialization of all the available remoteproc devices in the system. This doesn't allow the flexibility to initialize the remote cores needed as per use case. In order to provide flexibility, update 'rproc init' command to accept one more parameter with rproc id which when passed initializes only that specific core. If no id is passed, command will initializes all the cores which is compatible with the existing behaviour. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Update the power-domain-cells to 2 and add the permissions to each node. Mark the following nodes accessed by r5 as shared: - DDR node - main uart 0 Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
TISCI protocol supports for enabling the device either with exclusive permissions for the requesting host or with sharing across the hosts. There are certain devices which are exclusive to Linux context and there are certain devices that are shared across different host contexts. So add support for getting this information from DT by increasing the power-domain cells to 2. For keeping the DT backward compatibility intact, defaulting the device permissions to set the exclusive flag set. In this case the power-domain-cells is 1. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
TISCI protocol supports for enabling the device either with exclusive permissions for the requesting host or with sharing across the hosts. There are certain devices which are exclusive to Linux context and there are certain devices that are shared across different host contexts. So add support for getting this information from DT by increasing the power-domain cells to 2. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Certain drivers want to attach private data corresponding to each power domain. This data might be specific be to the drvier. So add a priv entry into the power_domain structure. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Release all the exclusive devices held by SPL. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Rather than simply parking the R5 core in WFE after starting up ATF on A53 instead use SYSFW API to properly shut down the R5 CPU cores as well as associated timer resources that were pre-allocated. This allows software further downstream to properly and gracefully bring the R5 cores back online if desired. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Any host while requesting for a device can request for its exclusive access. If an exclusive permission is obtained then it is the host's responsibility to release the device before the software entity on the host completes its execution. Else any other host's request for the device will be nacked. So add a command that releases all the exclusive devices that is acquired by the current host. This should be used with utmost care and can be called only at the end of the execution. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Add and expose a new processor shutdown API that wraps the two TISCI messages involved in initiating a core shutdown. The API will first queue a message to have the DMSC wait for a certain processor boot status to happen followed by a message to trigger the actual shutdown- with both messages being sent without waiting or requesting for a response. Note that the processor shutdown API call will need to be followed up by user software placing the respective core into either WFE or WFI mode. Signed-off-by: -
Sysfw provides an option for requesting exclusive access for a device using the flags MSG_FLAG_DEVICE_EXCLUSIVE. If this flag is not used, the device is meant to be shared across hosts. Once a device is requested from a host with this flag set, any request to this device from a different host will be nacked by sysfw. Current tisci driver enables this flag for every device requests. But this may not be true for all the devices. So provide a separate commands in driver for exclusive and shared device requests. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com>
-
- Jul 25, 2019
-
-
https://gitlab.denx.de/u-boot/custodians/u-boot-netTom Rini authored
- DaVinci emac DM work - NXP driver work - macb updates for RISC-V
-
H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by:
Emmanuel Vadot <manu@freebsd.org> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
-
Now that we removed all legacy boards selecting TI_EMAC we can completely convert the driver code to using the driver model. This patch also updates all remaining users of davinci_emac. Signed-off-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Adam Ford <aford173@gmail.com> #am3517-evm & da850-evm Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
-
We typically use same set of distro images (yocto, debian, fedora, etc.) on both QEMU RISC-V virt machine and SiFive Unleashed board. With growing kernel and ramdisk images, we need to re-adjust default U-Boot environment variables. The config header for QEMU RISC-V virt machine has been already updated to handle bigger kernel and ramdisk images hence this patch updates SiFive FU540 config header accordingly. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Tested-by:
-
Instead of depending on CONFIG_SYS_LITTLE_ENDIAN, we check at runtime whether underlying system is little-endian or big-endian. This way we are not dependent on any U-Boot specific OR compiler specific macro to check system endianness. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
The SiFive MACB ethernet has a custom TX_CLK_SEL register to select different TX clock for 1000mbps vs 10/100mbps. This patch adds SiFive MACB compatible string and extends the MACB ethernet driver to change TX clock using TX_CLK_SEL register for SiFive MACB. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
The LS1021A-TSN is a development board built by VVDN/Argonboards in partnership with NXP. It features the LS1021A SoC and the first-generation SJA1105T Ethernet switch for prototyping implementations of a subset of IEEE 802.1 TSN standards. Supported boot media: microSD card (via SPL), QSPI flash. Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which is 64 MB in size and has an erase sector size of 256KB (therefore, flashing the RCW would erase part of U-Boot). Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which is only 32 MB in size but has an erase sector size of 64KB (therefore the RCW image can be flashed without erasing U-Boot). To avoid the problems above, the U-Boot base address has been selected at 0x100000 (the start of the 5th 256KB erase sector), which works for all board revisions. Actually 0x40000 would have been enough, but 0x100000 is common for all Layerscape devices. eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is disabled. Signed-off-by:
Xiaoliang Yang <xiaoliang.yang_1@nxp.com> Signed-off-by:
Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by:
Jianchao Wang <jianchao.wang@nxp.com> Signed-off-by:
Changming Huang <jerry.huang@nxp.com> Signed-off-by:
Vladimir Oltean <olteanv@gmail.com> [Vladimir] Code taken from https://github.com/openil/u-boot (which itself is mostly copied from ls1021a-iot) and adapted with the following changes: - Add a008850 errata workaround - Converted eTSEC, MMC to DM to avoid all build warnings - Plugged in distro boot feature, including support for extlinux.conf - Added defconfig for QSPI boot - Added the board/freescale/ls1021atsn/README.rst for initial setup - Increased CONFIG_SYS_MONITOR_LEN so that the SPL malloc pool does not get overwritten during copying of the u-boot.bin payload from MMC to DDR. Acked-by:
Bin Meng <bmeng.cn@gmail.com> -
Due to a typo, "run qspi_bootcmd" and "env exists secureboot" got concatenated instead of being separated by a semicolon. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Acked-by: -
Now that we have added driver model support to the TSEC driver, convert ls1021atwr board to use it. This depends on previous DM series for ls1021atwr: http://patchwork.ozlabs.org/patch/561855/ Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: -
In the case of the tsec network driver, so far there has been no mainline user of DM_ETH where the DT bindings get used. In the case of the mdio bus, it looks like the "fsl,tsec-mdio" string was made up for the documentation, but there is no mainline code that parses the "compatible" property anyway. In both cases, there are no DT blobs that contain the old strings. So change the documentation to "fsl,etsec2" for the Ethernet ports and "fsl,etsec2-mdio" for the MDIO buses, which are strings that Linux also uses, at least for LS1021A. More compatible strings can be added once other (PowerPC) SoCs are migrated to DM_ETH. The current ls1021a.dtsi doesn't match what was documented for the MDIO buses anyway (the "compatible" is "gianfar" currently). This will be fixed in the next patch. Fixes: 69a00875 ("doc: dt-bindings: Describe Freescale TSEC ethernet controller") Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Acked-by: -
In tsec_init, the MAC address is retrieved from 2 different structures depending on whether DM_ETH is enabled or not. But since the field name is the same inside both structures, we can conditionally define the structure of the correct type and simplify the assignments. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
This replaces debug() calls with printf() so that it is immediately obvious from the console that something is wrong. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
This is a cosmetic patch that reorders variable definitions in the inverse order of their line length, where possible. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
By convention, the eTSEC MDIO controller nodes are defined in DT at 0x2d24000 and 0x2d50000, but actually U-Boot does not touch the interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM, MDIO_EMAPM). That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM, MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at the 0x520 offset. So shift the DT-defined register map by the offset of MDIO_MIIMCFG when mapping the MDIO bus registers. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
The point of this patch is to eliminate the use of the locally-defined "reg" variable (which interferes with next patch) and simplify the fallback to the default CONFIG_SYS_TBIPA_VALUE in case "tbi-handle" is missing. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Macb Ethernet controller requires a RX buffer of 128 bytes. It is highly sub-optimal for Gigabit-capable GEM that is able to use a bigger DMA buffer. Change this constant and associated macros with data stored in the private structure. RX DMA buffer size has to be multiple of 64 bytes as indicated in DMA Configuration Register specification. Signed-off-by:
-
DMA configuration was heavily dependent on the HW defaults, add function to properly set the required fields, including the new dma_burst_length. Signed-off-by:
-
GEM support higher DMA burst writes/reads than the default (4). add configuration structure with dma burst length so it could be applied later to DMA configuration. Signed-off-by:
-
This patch adds support for the sgmii phy interface, available only to DM users, dictated by current driver design. Signed-off-by:
-
macb.h provides macros for reading/setting bitfields, in macb registers and descriptors. use that instead of redefining them in the source file. Signed-off-by:
-
add support for clock rates higher than 2.4Mhz Signed-off-by:
-
Few registers and bits were added by Cadence and they were not updated in the headers. Take the latest definitions as defined in Linux header (5.1) that also includes some comments about existing registers. One register was improperly named (UR), fix that. Signed-off-by:
-
This binding documents two properties that describe the registers used to perform MUX selection. Signed-off-by:
Alex Marginean <alexm.osslist@gmail.com> Acked-by:
Bin Meng <bmeng.cn@gmail.com> -
This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
-
