Baruch Siach authored 6 years ago and Stefan Roese committed 6 years ago

Stefan is listed as a kirkwood maintainer since commit f822d857
(MAINTAINERS: Update Marvell custodianship).

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

Evgeni Dobrev authored 6 years ago and Stefan Roese committed 6 years ago

The default bootdelay of 3 seconds is good enough and there is no need
to duplicate it in CONFIG_EXTRA_ENV_SETTINGS.

Signed-off-by: Evgeni Dobrev <evgeni@studio-punkt.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Georgii Staroselskii authored 6 years ago and Bin Meng committed 6 years ago

These comments were copied from the Linux kernel driver in
drivers/platform/x86/intel_scu_ipc.c

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Georgii Staroselskii authored 6 years ago and Bin Meng committed 6 years ago

Now that we have I2C#6 working, it's time to add a corresponsing
ACPI binding.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Georgii Staroselskii authored 6 years ago and Bin Meng committed 6 years ago

Now that we have the pinctrl driver for Merrifield in place we can make
use of it and set I2C#6 pins appropriately.

Initial configuration came from the firmware.  Which quite likely has
been used in the phones, where that is not part of Atom peripheral, is
in use. Thus we need to override the leftover.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Georgii Staroselskii authored 6 years ago and Bin Meng committed 6 years ago

This API is going to be used to configure some pins that are protected
for simple modification.

It's not a comprehensive pinctrl driver but can be turned into one
when we need this in the future. Now it is planned to be used only
in one place. So that's why I decided not to pollute the codebase with a
full-blown pinctrl-merrifield nobody will use.

This driver reads corresponding fields in DT and configures pins
accordingly.

The "protected" flag is used to distinguish configuration of SCU-owned
pins from the ordinary ones.

The code has been adapted from Linux work done by Andy Shevchenko
in pinctrl-merrfifield.c

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix build warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Georgii Staroselskii authored 6 years ago and Bin Meng committed 6 years ago

This interface will be used to configure properly some pins on
Merrifield that are shared with SCU.

scu_ipc_raw_command() writes SPTR and DPTR registers before sending
a command to SCU.

This code has been ported from Linux work done by Andy Shevchenko.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Christian Gmeiner authored 6 years ago and Bin Meng committed 6 years ago

This will add support for a baud rate of 57600.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This patch adds mcf5441x eSDHC support for the mcf5441x family.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>

On a
	u32 val = __sw32(*addr);

multiple memory accesses are not welcome, since "addr" may
be an IO peripheral register address.
This patch changes __sw16/32 to perform a single memory
access for the source value.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>

Signed-off-by: Angelo Dureghello <angelo@sysam.it>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

The Gen2 TMU is fed with fixed 32.5 MHz signal from CP .
This is then divided by 4 in TMU. Fix the timer clock
setting in Gen2.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

Replace those two functions with generic ones by defining the
timer macros in include/config/*.h .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

The code uses all in all three TMU registers, drop the massive
register layout structures and just define the required timer
registers and use them throughout the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

The header contains only the TMU register layout, just inline it
into the TMU timer implementation and drop the header completely.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

The R-Car Gen2 feeds the TMU with CONFIG_SYS_CLK_FREQ / 2,
while the old SH parts use CONFIG_SYS_CLK_FREQ directly.
Just put this into the TMU implementation and drop the
CONFIG_SH_TMU_CLK_FREQ config option.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

This function just returns CONFIG_SH_TMU_CLK_FREQ, use the constant
directly instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

These functions are always called for timer = 0, so drop the
timer check. Since these functions are called from one place
only and they are reduced to one line of code, just inline
them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

The tmu_bit value evaluates to (ffs(4) >> 1) - 1 = (3 >> 1) - 1 = 0.
Just drop the tmu_bit completely as well as CONFIG_SYS_TMU_CLK_DIV.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

This constant is always 4 , for all boards that exist. Define it
once in arch/sh/lib/time.c and remove it from the configs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

Drop the macro as it is never used and it collides with sh_eth.h macros.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Marek Vasut authored 6 years ago and Marek Vasut committed 6 years ago

Drop the macro as it is defined in sh7723.h already.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Patrice Chotard authored 6 years ago and Marek Vasut committed 6 years ago

Add vbus-supply regulator support.
On some board vbus is not controlled by the phy but by
an external regulator.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Dalon Westergreen authored 6 years ago and Marek Vasut committed 6 years ago

The dtb should be embedded in the u-boot-spl image so that
the CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it.

This also affects the main u-boot image, so adjust
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot.img which now
also includes the dtb.

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>

Dalon Westergreen authored 6 years ago and Marek Vasut committed 6 years ago

Incorrect type of size variable results in 0 being
returned for sdram sizes greater than or equal to
4GB.

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>

Dalon Westergreen authored 6 years ago and Marek Vasut committed 6 years ago

Stratix10 combines the u-boot-spl image into the fpga configuration
bitstream so that the SDM can load the processors memory.  This
process requires a hex format of the u-boot-spl image.
CONFIG_SPL_TARGET is set to "spl/u-boot-spl.hex"

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>

Dalon Westergreen authored 6 years ago and Marek Vasut committed 6 years ago

Some devices, namely Intel's stratix10 SoC, require u-boot-spl in
a hex format.  This patch adds spl/u-boot-spl.hex as a possible
target.

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>

Ley Foon Tan authored 6 years ago and Marek Vasut committed 6 years ago

This changes the driver to use dev_read_addr() which is safe both for
flat trees and live trees.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Ley Foon Tan authored 6 years ago and Marek Vasut committed 6 years ago

Add code to reset all reset signals as in gpio DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Ley Foon Tan authored 6 years ago and Marek Vasut committed 6 years ago

Enabled get_function support for dwapb where the function will
return the state of GPIO port.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

This commit is breaking several variants of da850, so:

This reverts commit 5f389201.

Signed-off-by: Tom Rini <trini@konsulko.com>

I added in the CONFIG_MISC_INIT_R line by mistake when applying the
previous patch, fix.

Signed-off-by: Tom Rini <trini@konsulko.com>

Stefan Roese authored 6 years ago and Heiko Schocher committed 6 years ago

I just stumbled over some cluttered UBIFS messages. It seems some
newline chars are missing in the current U-Boot UBI source.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>