Adam Ford authored 7 years ago and Tom Rini committed 7 years ago

To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.

There are some spacing issues in the patch, but they appear to be
present in the Linux source files.  I'll try to get to fixing them there,
and do a future re-sync at a later date.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>

Ulf Magnusson authored 7 years ago and Tom Rini committed 7 years ago

Corresponds to 375506d (File writing nit) from upstream
(https://github.com/ulfalizer/Kconfiglib

).

Adds proper 'imply' support and fixes a few minor issues, one of which
previously triggered the following weird warning:

  configs/taurus_defconfig: /tmp/tmpisI45S:6: warning: assignment to SPL_LDSCRIPT changes mode of containing choice from "arch/$(ARCH)/cpu/u-boot-spl.lds" to "y"

The change in 8639f69a (genconfig.py: Print defconfig next to warnings)
was reapplied.

tools/moveconfig.py previously depended on a hack that merged 'select's
with 'imply's. It was modified to look at the union of
Symbol.get_selected_symbols() and Symbol.get_implied_symbols(), which
should give the same behavior.

tools/genboardscfg.py was verified to produce identical board.cfg's
before and after the change.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>

Heinrich Schuchardt authored 7 years ago and Tom Rini committed 7 years ago

Checkpatch can use two dictionaries for finding typos:
* scripts/spelling.txt
* /usr/share/codespell/dictionary.txt
  which comes with package codespell and is selected by parameter
  --codespell

If the file scripts/spelling.txt is missing, a warning is shown.

Add the spelling.txt file from the Linux kernel 4.13 source.

We can later add our own typo corrections.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Dan Murphy <dmurphy@ti.com>

Stephen Warren authored 7 years ago and Tom Rini committed 7 years ago

The current code wraps a pre tag inside an a tag. For some reason, this
causes at least Firefox to attempt to drag the pre section content when
using a mouse drag to select text. Re-order the tags so that the text can
be selected using the mouse, at least if you start the drag outside the
text (after the end of the line, for example).

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Stephen Warren authored 7 years ago and Tom Rini committed 7 years ago

Some tests use external tools (executables) during their operation. Add
a test.py mark to indicate this. This allows those tests to be skipped if
the required tool is not present.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Stephen Warren authored 7 years ago and Tom Rini committed 7 years ago

When skipping tests, explicitly mention the board type or config option
that caused the skip. This will help people understand/fix any issues.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Stephen Warren authored 7 years ago and Tom Rini committed 7 years ago

Some tests rely on external tools. Mention these in the test/py README.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

On ARCH_OMAP2PLUS platforms we know what the DDR layout is going to be,
and that it is safe to use SPL_STACK_R and provide a default value for
it.  select this and re-sync the defconfigs.

Signed-off-by: Tom Rini <trini@konsulko.com>

Adam Ford authored 7 years ago and Tom Rini committed 7 years ago

With DM now enabled with the device tree pulled from Linux, we can
enable DM_I2C in U-Boot.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add DM_I2C_COMPAT to da850_am18xxevm to fix warning]
Signed-off-by: Tom Rini <trini@konsulko.com>

Adam Ford authored 7 years ago and Tom Rini committed 7 years ago

There is a discrepency between U-Boot and Linux on the partition map.
This enabes the MTD parts to pass MTD partition information from U-Boot to
Linux.  Linux already has a pending patch to enable MTD PARTS in
davinci_all_defconfig

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>

Adam Ford authored 7 years ago and Tom Rini committed 7 years ago

With the device tree ported and DM compatible drivers, enable:
OF_CONTROL, DM_SPI, DM_SPI_FLASH and DM_SERIAL

Note: DM_SERIAL is not enabled for da850evm_direct_nor_defconfig
yet.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>

Adam Ford authored 7 years ago and Tom Rini committed 7 years ago

The DM support is already in the driver, so add
da830-spi to the compatible list.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>

Adam Ford authored 7 years ago and Tom Rini committed 7 years ago

A few small additional items are needed to support DM_SPI and
DM_SERIAL, so those were added to da850-evm-u-boot.dtsi

Signed-off-by: Adam Ford <aford173@gmail.com>

Masahiro Yamada authored 7 years ago and Jaehoon Chung committed 7 years ago

The MMC framework in U-Boot does not support a systematic API for
timing switch like mmc_set_timing() in Linux.

U-Boot just provides a hook to change the clock frequency via
mmc_set_clock().  It is up to drivers if additional register
settings are needed.

This driver needs to set a correct timing mode into a register when
it migrates to a different speed mode.  Only increasing clock frequency
could result in setup/hold timing violation.

The timing mode should be decided by checking MMC_TIMING_* like
drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not
supported by U-Boot for now.  Just use mmc->clock to decide the
timing mode.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Seung-Woo Kim authored 7 years ago and Jaehoon Chung committed 7 years ago

If there are no CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR and CONFIG_SPL_OS_BOOT,
there is unused-function build warning. Add __maybe_unused macro
to remove the warning.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Marek Vasut authored 7 years ago and Jaehoon Chung committed 7 years ago

Add initial support for setting the vqmmc regulator. Since we do not
support 1V8 modes, set the regulator to 3V3 and enable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Marek Vasut authored 7 years ago and Jaehoon Chung committed 7 years ago

Old version of the uniphier-sd 64bit IO support patchset V1 was
applied by the maintainer, update the uniphier-sd.c with the
changes from the V3 of the patchset.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Patrice Chotard authored 7 years ago and Jaehoon Chung committed 7 years ago

This patch adds SD/MMC support for STM32H7 SoCs.

Here is an extraction of SDMMC main features, embedded in
STM32H7 SoCs.
The SD/MMC block include the following:
 _ Full compliance with MultiMediaCard System Specification
   Version 4.51. Card support for three different databus modes:
   1-bit (default), 4-bit and 8-bit.
 _ Full compatibility with previous versions of MultiMediaCards
   (backward compatibility).
 _ Full compliance with SD memory card specifications version 4.1.
   (SDR104 SDMMC_CK speed limited to maximum allowed IO speed,
    SPI mode and UHS-II mode not supported).
 _ Full compliance with SDIO card specification version 4.0.
   Card support for two different databus modes: 1-bit (default)
   and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO
   speed, SPI mode and UHS-II mode not supported).
 _ Data transfer up to 208 Mbyte/s for the 8 bit mode.
   (depending maximum allowed IO speed).
 _ Data and command output enable signals to control external
   bidirectional drivers.

The current version of the SDMMC supports only one SD/SDIO/MMC card
at any one time and a stack of MMC Version 4.51 or previous.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

It is caused from asm/io.h declare different input type.

Signed-off-by: rick <rick@andestech.com>

During using dwc2 usb gadget, if usb message size is too small,
following cache misaligned warning is shown:

   CACHE: Misaligned operation at range [bfdbcb00, bfdbcb04]

Align size of invalidating dcache before starting DMA to remove the
warning.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

The choice of "USB keyboard polling" cannot be optional as without
one mechanism being set, it just doesn't work. Set the default one
to CONFIG_SYS_USB_EVENT_POLL.

Fixes: ecad7051 ("configs: Migrate all of the existing USB symbols, except fastboot")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Update the generic EHCI driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Update the DWC2 USB driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Update the Rockchip xhci wrapper driver to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

When EHCD and xHCD are enabled at the same time, USB storage device
driver will fail to read/write from/to the storage device attached
to the xHCI interface, due to its transfer blocks exceeds the xHCD
driver limitation.

With driver model, we have an API to get the controller's maximum
transfer size and we can use that to determine the storage driver's
capability of read/write.

Note: the non-DM version driver is still broken with xHCD and the
intent here is not to fix the non-DM one, since the xHCD itself is
already broken in places like 3.0 hub support, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

This adds a new memeber max_xfer_blk in struct us_data to record
the maximum number of transfer blocks for the storage device.

It is set per HCD setting, and so far is to 65535 for EHCD and 20
for everything else.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

EHCD can handle any transfer length as long as there is enough free
heap space left, hence set the theoretical max number SIZE_MAX.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

xHCD allocates one segment which includes 64 TRBs for each endpoint
and the last TRB in this segment is configured as a link TRB to form
a TRB ring. Each TRB can transfer up to 64K bytes, however data
buffers referenced by transfer TRBs shall not span 64KB boundaries.
Hence the maximum number of TRBs we can use in one transfer is 62.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

The HCD may have limitation on the maximum bytes to be transferred
in a USB transfer. USB class driver needs to be aware of this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

The Linux kernel driver sets the number of event segments and entries
to 1 , while the initial import of the xhci code set that values to 3
for reasons unknown. While most controllers are fine with more event
segments with more entries, there are standard-conformant controllers
(ie. Renesas RCar xHCI) which only support 1 event segment.

Set the number of event segments and event entries back to 1 to allow
such controllers to work with U-Boot xHCI stack. Note that the Renesas
controller correctly indicates ERST Max = 1 in HCSPARAMS2[7:4] .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>

Heinrich Schuchardt authored 7 years ago and Tom Rini committed 7 years ago

memset(newpart, '\0', sizeof(newpart));
only initializes the firest 4 or 8 bytes of *newpart and not the whole
structure disk_part.

We should use sizeof(struct disk_part).

Instead of malloc and memset we can use calloc.

Identified by cppcheck.

Fixes: 09a49930 GPT: read partition table from device into a data structure
Reported-by: Coverity (CID: 167228)
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

Marek Vasut authored 7 years ago and Stefan Roese committed 7 years ago

The status register is optional in the AMD command sets, but it's
presence can be checked by reading out CFI table entry 0xc bit 0.
If the register is present, prefer using it's bit 7 to determine
if the flash is busy over reading the flash ; this is needed ie.
on Hyperflash memories.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Marek Vasut authored 7 years ago and Stefan Roese committed 7 years ago

Embed the flash base into struct flash_info instead of having ad-hoc
static array in the code. This does not only remove static variable,
but also allows CFI-like controllers, ie. HyperFlash ones, to use most
of the CFI flash code by populating the flash_info with matching base
address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Baruch Siach authored 7 years ago and Stefan Roese committed 7 years ago

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

Baruch Siach authored 7 years ago and Stefan Roese committed 7 years ago

The ClearFog Base boot from UART when setting the DIP switches to 01001.
Unfortunately, the SPL code sometimes fails to detect the UART boot
method at run-time. Add an alternative SAR UART boot value to fix this.

Note that this alternative value is not documented (Armada 38x Hardware
Specifications, Table 48). But experimentations showed it on the
ClearFog Base.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>