- Jan 12, 2021
-
-
Include the SoC U-boot DTS in each am335x-<board>-u-boot.dtsi. Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
The patch adds support for TI gate clock binding. The code is based on the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/gate.txt Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
The patch adds support for TI divider clock binding. The driver uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/divider.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/divider.txt Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM33xx device. The AM33xx device integrates five different DPLLs: * Core DPLL * Per DPLL * LCD DPLL * DDR DPLL * MPU DPLL The patch adds support for the compatible strings: * "ti,am3-dpll-core-clock" * "ti,am3-dpll-no-gate-clock" * "ti,am3-dpll-no-gate-j-type-clock" * "ti,am3-dpll-x2-clock" The code is loosely based on the drivers/clk/ti/dpll.c drivers of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/dpll.txt Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
Add missing DPLL_EN_FAST_RELOCK_BYPASS macro. Used to put the DPLL in idle bypass fast relock mode. Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
The driver manages a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. It uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/mux.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/mux.txt Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
It returns the rate which will be set if you ask clk_set_rate() to set that rate. It provides a way to query exactly what rate you'll get if you call clk_set_rate() with that same argument. So essentially, clk_round_rate() and clk_set_rate() are equivalent except the former does not modify the clock hardware in any way. Signed-off-by:
Dario Binacchi <dariobin@libero.it> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Sean Anderson <seanga2@gmail.com>
-
There have been several changes to the am33xx.dtsi, so this patch re-syncs it with Linux. Let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as documented in Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel. With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. The am33xx-clock.dtsi file is the same as that of the Linux kernel, except for the reg property of the node l4-wkup-clkctrl@0. As for the am33xx.dtsi file, all the devices with drivers not yet implemented and those I was able to test with this patch have been moved to am33xx-l4.dtsi. In case of any regressions, problem devices can be reverted by moving them back and removing the related interconnect target module node. Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
We can handle the sysc interconnect target module in a generic way for many TI SoCs. Initially let's just enable domain clocks before the children are probed. The code is loosely based on the drivers/bus/ti-sysc.c of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/bus/ti-sysc.txt Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
Add support for PRUSS SYSC type: The PRUSS module has a SYSCFG which is unique. The SYSCFG has two additional unique fields called STANDBY_INIT and SUB_MWAIT in addition to regular IDLE_MODE and STANDBY_MODE fields. Add the bindings for this new sysc type. Add support for MCAN on dra76x: The dra76x MCAN generic interconnect module has a its own format for the bits in the control registers. Signed-off-by:
Dario Binacchi <dariobin@libero.it>
-
Export routines that can be used by other drivers avoiding duplicating code. Signed-off-by:
Dario Binacchi <dariobin@libero.it> Reviewed-by:
Simon Glass <sjg@chromium.org>
-
As more and more LINUX drivers are modified to use asynchronous probing instead of synchronous probing, relying on device names being equal in U-Boot and LINUX is not possible anymore. This is also true for block device names like mmc0, mmc1 ect. With LINUX kernel commit a1a4891 the probing type for the sdhci-omap driver has been set to asynchronous mode too (probe_type is now PROBE_PREFER_ASYNCHRONOUS). In the case of the PDU001 board this results in the devices mmc0 and mmc1 being swapped between U-Boot and LINUX. Device mmc0 in U-Boot becomes mmc1 in LINUX an vice versa. Hence using device name identifiers with LINUX kernel parameter root does not work anymore. This patch changes the LINUX kernel boot parameter root to use the pseudo (since we use MBR not GPT) partition UUID to locate the partition hosting the root file system. Signed-off-by:
Felix Brack <fb@ltec.ch>
-
Lokesh Vutla authored
Add board detection support for K2G ICE with FlagChip 1GHz silicon. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
-
Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 4266MTs DDR configuration. Signed-off-by:
Praneeth Bajjuri <praneeth@ti.com> Signed-off-by:
Kevin Scholz <k-scholz@ti.com>
-
McSPI IP provides per CS specific speed and mode selection. Therefore it is possible to apply these settings only after CS is known. But set_speed and set_mode can be called without bus being claimed, this would lead driver to set up wrong CS (or previously used CS). Fix this by apply set_speed and set_mode only if bus is already claimed. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Tested-by:
Miquel Raynal <miquel.raynal@bootlin.com>
-
struct ti_qspi_priv->max_hz is declared as unsigned int, so the following error path check will always be false, even when "spi-max-frequency" property is invalid/missing: priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { ... } Replace the fdtdec call with dev_read_u32_default() and use 0 as the default value. Error out if max_hz is zero. Signed-off-by:
Ovidiu Panait <ovidiu.panait@windriver.com>
-
The value of input pin for bank > 0 is always 0 for input subcommand. The reason is that gpio_bank variable is computed only for invert and output subcommands (it depends on number of arguments). The default value of zero causes to shift the mask away for banks > 0. Please note that info subcommand works as expected, because the input pin values are accessed differently. Fixes: 61c1775f ("gpio: tca642x: Add the tca642x gpio expander driver") Cc: Dan Murphy <dmurphy@ti.com> Signed-off-by:
Tomas Novotny <tomas@novotny.cz>
-
In include/dfu.h, if CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then it is defined as CONFIG_SYS_DFU_DATA_BUF_SIZE. This is 128 KiB for a53 core and 20 KiB for r5 core. If a larger file is transferred using dfu then it fails. CONFIG_SYS_DFU_DATA_BUF_SIZE can not be increased as there is not enough heap memory to be allocated for the buffer in case of R5 spl. Fix this by defining CONFIG_SYS_DFU_MAX_FILE_SIZE as the default CONFIG_SYS_DFU_DATA_BUF_SIZE value. Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com>
-
The sequence number assigned for USB subsystem in a uclass is dependent on the order of occurrence in the device tree. If the dr_mode of USB3SS0 controller is varied then the sequence number of USB3SS1 controller also changes. If aliases are added then sequence numbers are assigned using the alias number. This makes the sequence number of USB3SS1 controller independent of USB3SS0 controller's dr_mode. Therefore, add aliases to fix the sequence number assigned to the USB subsystems. Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com>
-
USB3SS0 controller is to be used as a host in U-boot. Fix it by changing the dr_mode to host. Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com>
-
It has been observed that setting SERDES0 lane mux to USB prevents USB 2.0 operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is used in USB 2.0 only mode solves this issue. However, for USB3.0+2.0 operation this issue is not present. Implement this workaround by writing 1 to LANE_FUNC_SEL field in CTRLMMR_SERDES0_CTRL register. Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com>
-
- Jan 11, 2021
-
-
Tom Rini authored
Signed-off-by:
Tom Rini <trini@konsulko.com>
-
Tom Rini authored
Signed-off-by:
Tom Rini <trini@konsulko.com>
-
- Jan 08, 2021
-
-
On the XEA board (imx28) one needs in the SPL support for GPIO, MMC and SPI. Two last ones are necessary for booting the device. The GPIO support allows deciding which medium will be used. For example the GPIO DTS node (gpio@0 at imx28.dtsi) has pinctrl parent (pinctrl@80018000) for which we don't need driver asigned for correct operation. In the spl/dts/dt-platdata.c the gpio@0 has index 4 and its parent - pinctrl@80018000 has index 5. In the bind_drivers_pass() function (at drivers/core/lists.c) call to device_bind_by_name() for `fsl_imx23_pinctrl` returns -2, which is expected. With current setup - when the SPL_OF_PLATDATA_PARENT=y The gpio@0 node with index 4 is skipped as its parent with 5 is not yet bound. It cannot be as we don't need and provide the driver for it. As a result the gpio@0 is never bound and we end up with bricked board in the SPL stage. When CONFIG_SPL_OF_PLATDATA_PARENT is NOT set, all entries from spl/dts/dt-platdata.c are scanned in ascending index order, so gpio@0 is properly initialized. For `fsl_imx_pinctrl` we simply check 10 times if the driver for is available (which is not) and exit. As a result the GPIOs are initialized and can be used in early SPL stage. This commit fixes XEA regression introduced with e41651ff. Signed-off-by:
Lukasz Majewski <lukma@denx.de> Reviewed-by:
Simon Glass <sjg@chromium.org>
-
The usage of the preboot feature is now controlled via a separate Kconfig option - namely CONFIG_USE_PREBOOT. It must be enabled for preboot code executing commands now defined in CONFIG_PREBOOT (also moved to the Kconfig). After defining both CONFIG_USE_PREBOOT and CONFIG_PREBOOT in imx28_xea_defconfig the define of CONFIG_PREBOOT shall be removed from xea.h as it is redundant. Signed-off-by:
Lukasz Majewski <lukma@denx.de>
-
On the imx287 pin GPMI_WRN (GPIO0_25) no PullUP is available that can be enabled. To get the same behavior for both boot select pins (i.e. GPIO0_2{35}) disable pull UPs on both. Signed-off-by:
Lukasz Majewski <lukma@denx.de>
-
SPI flash on this machine is located on bus 1, default to using bus 1 for SPI flash and stop aliasing it to bus 0. Signed-off-by:
Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by:
Simon Glass <sjg@chromium.org> Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
-
- Jan 06, 2021
-
-
Tom Rini authored
Merge tag 'xilinx-for-v2021.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.04 arm64: - DT updates microblaze: - Add support for NOR device support spi: - Fix unaligned data write issue nand: - Minor code change xilinx: - Fru fix in limit calculation - Fill git repo link for all Xilinx boards video: - Add support for seps525 spi display tools: - Minor Vitis file support cmd/common - Minor code indentation fixes serial: - Uartlite debug uart initialization fix
-
https://gitlab.denx.de/u-boot/custodians/u-boot-stmTom Rini authored
- Fix GPIO hog flags on DHCOM boards
-
The GPIO hog flags are ignored by gpiolib-of.c now, set the flags to 0. Since GPIO_ACTIVE_HIGH is defined as 0, this change only increases the correctness of the DT. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by:
Patrice Chotard <patrice.chotard@st.com> Reviewed-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
-
The GPIO hog flags are ignored by gpiolib-of.c now, set the flags to 0. Due to a change in gpiolib-of.c, setting flags to GPIO_ACTIVE_LOW and using output-low DT property leads to the GPIO being set high instead. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by:
Patrice Chotard <patrice.chotard@st.com> Reviewed-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
-
git://git.denx.de/u-boot-dmTom Rini authored
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
-
- Jan 05, 2021
-
-
Tom Rini authored
Prepare v2021.01-rc5 Signed-off-by:
Tom Rini <trini@konsulko.com>
-
-
Simon Glass authored
Some of these tests don't actually check anything. Add a few more checks to complete the tests. Also add a simple scan test that does the basics. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
Simon Glass authored
Move the tests related to scanning into their own class, updating them to avoid using dtb_platdata as a pass-through. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
Simon Glass authored
Before expanding the scanning features any more, move this into a separate file. This will make it easier to maintain in the future. In particular, it reduces the size of dtb_platdata.py and allows us to add tests specifically for scanning, without going through that file. The pieces moved are the Driver class, the scanning code and the various naming functions, since they mostly depend on the scanning results. So far there is are no separate tests for src_scan. These will be added as new functionality appears. This introduces no functional change. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
Simon Glass authored
This has not been needed since parent information was added and we started using indicies for references to other drivers instead of pointers. It was kept around in the expectation that it might be needed later. However with the latest updates, it doesn't seem likely that we'll need this in the foreseeable future. Drop dm_populate_phandle_data() from dtoc and driver model. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
Simon Glass authored
Previously we had to worry about nodes being output before those that they depended on, thus causing build errors. So the current algorithm is careful to output nodes in the right order. We now use a different method for outputting phandles that does not involve pointers. Also we plan to add a 'declarations' header file to declare all drivers as 'extern'. Update the code to drop the dependency checking and output in a simple loop. This makes the output easier to follow since drivers are in order of thier indices (0, 1, ...), which is also the order it appears in in the linker list. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
Simon Glass authored
The base directory of U-Boot, where the source is, it currently calculated from the directory of the dtb_platdata.py script. If this is installed elsewhere that will not work. Also it is inconvenient for tests. Add a parameter to allow specifying this base directory. To test this, pass a temporary directory with some files in it and check that they are passed to scan_driver(). Signed-off-by:
Simon Glass <sjg@chromium.org>
-