- Oct 11, 2019
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AM57xx-IDK boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by:Tero Kristo <t-kristo@ti.com>
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Add support for CDCE913/925/937/949 family of devices. These are modular PLL-based low cost, high performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. The initial version of the driver does not support programming of the PLLs, and thus they run in the bypass mode only. The code is loosely based on the linux kernel cdce9xx driver. Signed-off-by: -
Use the driver name to get ti_sci handle rather than relying on just the FIRMWARE uclass. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Enable CONFIG_DISPLAY_CPUINFO so that cpuinfo is printed during boot. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Enable CONFIG_DISPLAY_CPUINFO so that cpuinfo is printed during boot. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Print the board name and ver along with the DT Model. While at it print the ver for all the detected daughter cards. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Add support for printing CPU info for all K3 devices. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
J721E uses TISCI protocol to reset the device and does not support PSCI reset. So disable PSCI reset. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
AM65x uses TISCI protocol to reset the device and does not support PSCI reset. So disable PSCI reset. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Power-domain is enabled by default in device_probe. am654 mmc driver is enabling power-domain again in probe. As the second call is redundant, drop power_domain_on from probe. Tested-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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When running 'run_fit' the FIT file should have been loaded at 'addr_fit', although at this point they should be the same use this variable instead of 'loadaddr'. Signed-off-by:Andrew F. Davis <afd@ti.com>
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- update partition table - remove env partitions - dts: add new interfaces (uart2, extra gpio-key) remove unneeded entries update nand timings for performance improvement - defconfig: adapt configurations to suit DM remove unneeded configs - am335x_guardian.h: remove mmc boot Signed-off-by:Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> Reviewed-by:
Tom Rini <trini@konsulko.com>
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- add BOARD_LATE_INIT function calls in board.c - add swi_status detection in board.c - mux: add guardian interfaces to single pinmux structure - am33xx, kconfig: add BOARD_LATE_INIT for GUARDIAN board Signed-off-by:
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If the ECC is enabled over the entire memory region, we need to ensure the printf/put calls do not modify the stack after ECC is disabled. Moved the printf/put statements after ECC is enabled. Signed-off-by:
Krunal Bhargav <k-bhargav@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Before the priming begins, we need to disable RMW (Read Modify Write) and disable ECC verification for read accesses. By default, the EMIF tool enables RMW and read accesses in the EMIF_ECC_CTRL_REG. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
If ECC is enabled, we need to ensure interleaving is disabled for higher address space. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
ecc_address_range registers contains the start address and end address of the DDR address space. But the ddr cmd driver is assuming the register contains the start address and size of the DDR address space. Because of this some valid ecc addresses are errored out as invalid address. Fix this calculation. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
ecc_address_range registers contains the start address and end address of the DDR address space. But the ddr driver is assuming the register contains the start address and size of the DDR address space. Because of this the ecc enabling is failing for the 2nd range of ecc addresses. Fix this calculation. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Add README file explaining the build and boot procedure for J721E evm. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. In order to view the code loaded by the U-Boot by remote cores, U-Boot should configure the memory region with right memory attributes. Right now U-Boot carves out a memory region which is not sufficient for all the images to be loaded. So, increase this carve out region by 256MB. Signed-off-by:
Kedar Chitnis <kedarc@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
The A53 U-Boot code can load and boot the MCU domain R5F cores (either a single core in LockStep mode or 2 cores in Split mode) to achieve various early system functionalities. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code loaded by U-Boot. These regions are currently limited to 0xa0000000 to 0xa2100000 as per the DDR carveouts assigned for these R5F cores in the overall DDR memory map. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
The A53 U-boot can support early booting of the MCU R5F remote processor(s) from U-boot prompt to achieve various system usecases before booting the Linux kernel. Update the default BOOTCOMMAND to provide an automatic and easier way to start the MCU R5F cores through added environment variables. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Enable the R5F remoteproc driver for the AM65x GP EVM so that the MCU domain R5F cores can be booted from A53 U-boot. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
The A72 U-boot can support early booting of any of the R5F or C66x or C71x remote processors from U-boot prompt to achieve various system usecases before booting the Linux kernel. Update the default BOOTCOMMAND to provide an automatic and easier way to start various remote processors through added environment variables. Signed-off-by:
Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by:
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Enable R5F and DSP remoteproc drivers for j721e running on a72. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Add support to boot the MCU domain R5F Core0 remoteproc at U-boot prompt on the AM65x EVM boards by using the 'boot_rprocs' and other env variables defined in the common environment file k3_rproc.h, and updating the 'DEFAULT_RPROCS' macro. The default configuration is to use the MCU R5F in Split mode, so both the R5F Core0 and Core1 are started before loading and booting the Linux kernel using the following firmware: MCU R5FSS0 Core0 (Split) : 0 /lib/firmware/am65x-mcu-r5f0_0-fw MCU R5FSS0 Core1 (Split) : 1 /lib/firmware/am65x-mcu-r5f0_1-fw The MCU R5FSS was initially running the R5 SPL in LockStep mode with ATCM disabled, and is actually shutdown to enable it to be reconfigured and booted by either A53 U-Boot or Linux kernel in remoteproc mode and using ATCM. The MCU R5FSS would need to be reconfigured for Lockstep mode through DT if a fault-tolerant/safety application were to be run on the cluster with the DEFAULT_RPROCS macro updated to remove the Core1 firmware. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Add support to boot some remoteprocs at U-boot prompt on the J721E EVM boards by using the 'boot_rprocs' and other env variables defined in the common environment file k3_rproc.h, and updating the 'DEFAULT_RPROCS' macro. The list of R5F cores to be started before loading and booting the Linux kernel are as follows, and in this order: Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7-main-r5f0_1-fw Main R5FSS1 (LockStep) : 4 /lib/firmware/j7-main-r5f1_0-fw The MCU R5FSS0 and Main R5FSS1 are currently in LockStep mode, so the equivalent Core1 rprocs (rproc #1 and #5) are not included. The Main R5FSS0 Core0 (rproc #2) is already started by R5 SPL, so is not included in the list either. The DSP cores are started in the following order before loading and booting the Linux kernel: C66_0: 6 /lib/firmware/j7-c66_0-fw C66_1: 7 /lib/firmware/j7-c66_1-fw C71_0: 8 /lib/firmware/j7-c71_0-fw The order of the rprocs to boot can be changed at runtime if desired by overwriting the 'rproc_fw_binaries' environment variable at U-boot prompt. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Add a new file include/environment/ti/k3_rproc.h that defines common environment variables useful for booting various remote processors from U-Boot. This file is expected to be included in the board config files with the EXTRA_ENV_RPROC_SETTINGS added to CONFIG_EXTRA_ENV_SETTINGS and DEFAULT_RPROCS macro overwritten to include the actual list of processors to be booted. The 'boot_rprocs' variable just needs to be added to the board's bootcmd to automatically boot the processors, and runtime control can be achieved through the 'dorprocboot' variable. The variables are currently defined to use MMC as the boot media, and can be expanded in the future to include other boot media. The immediate usage is intended for K3 J721E SoCs. Signed-off-by:
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The AM65x SoCs has a single dual-core Arm Cortex-R5F processor subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN voltage domain containing the next-generation C711 CPU core. The subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of L2 configurable SRAM/Cache. This subsystem has a CMMU but is not used currently. The inter-processor communication between the main A72 cores and the C711 processor is achieved through shared memory and a Mailbox. Add the DT node for this DSP processor sub-system in the common k3-j721e-main.dtsi file. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional 288 KB of L2 configurable SRAM/Cache. These subsystems do not have an MMU but contain a Region Address Translator (RAT) sub-module for translating 32-bit processor addresses into larger bus addresses. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Add the DT nodes for these DSP processor sub-systems in the common k3-j721e-main.dtsi file. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for these two MAIN domain R5F cluster/subsystems, the two R5 cores are each added as child nodes to the corresponding main cluster node. Configure SS0 in split mode an SS1 in lockstep mode, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Certain SoCs with K3 architecture have integrated a C66 Corepac DSP subsystem and an advanced C71 DSPs. Introduce a remoteproc driver that that does take care of loading an elf to any of the specified DSPs and start it. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: -
Some Texas Instruments K3 family of SoCs have one of more Digital Signal Processor (DSP) subsystems that are comprised of either a TMS320C66x CorePac and/or a next-generation TMS320C71x CorePac processor subsystem. Add the device tree bindings document for the C66x DSP devices on these SoCs. The added example illustrates the DT nodes for the first C66x DSP device present on the K3 J721E family of SoCs. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
SoCs with K3 architecture have an integrated Arm Cortex-R5F subsystem that is comprised of dual-core Arm Cortex-R5F processor cores. This R5 subsytem can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - TCMA and TCMB. Add a remoteproc driver to support this subsystem to be able to load and boot the R5 cores primarily in LockStep mode or split mode. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: -
The Texas Instruments K3 family of SoCs have one of more dual-core Arm Cortex R5F processor subsystems/clusters (R5FSS). Add the device tree bindings document for these R5F subsystem devices. These R5F processors do not have an MMU, and so require fixed memory carveout regions matching the firmware image addresses. The nodes require more than one memory region, with the first memory region used for DMA allocations at runtime. The remaining memory regions are reserved and are used for the loading and running of the R5F remote processors. The added example illustrates the DT nodes for the single R5FSS device present on K3 AM65x family of SoCs. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Power domain for the remote cores needs to be handled in a right sequence as mandated by the spec. Introduce tisci helper apis that can control power-domains of remote cores. TISCI clients can use this api and control the remote cores power domain instead of hooking it to power-domain layer. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Introduce rproc_elf_get_boot_addr() that returns the entry point of the elf file. This api auto detects the 64/32 bit elf file and returns the boot addr accordingly. Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com> -
Introduce a common remoteproc elf loader and checker functions that automatically detects the 64 bit elf file or 32 bit elf file and loads/checks the sections accordingly. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
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