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  1. Jul 10, 2021
    • André Przywara's avatar
      sunxi: clock: H6/H616: Fix PLL clock factor encodings · f9d13247
      André Przywara authored
      
      Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
      which we were missing on two occasions.
      
      This fixes the MMC clock setup on the H6, which could be slightly off due
      to the wrong parent frequency:
      mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000
      
      Also the CPU frequency (PLL1) was a tad too high before.
      
      For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
      itself, not in the bit field macro. Move this there to be aligned with
      what the other SoCs and other PLLs do.
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
      f9d13247
    • Paul Kocialkowski's avatar
      phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB · 0d5824cb
      Paul Kocialkowski authored and André Przywara's avatar André Przywara committed
      
      Recent Allwinner platforms (starting with the H3) only use the MUSB
      controller for peripheral mode and use HCI for host mode. As a result,
      extra steps need to be taken to properly route USB signals to one or
      the other. More precisely, the following is required:
      * Routing the pins to either HCI/MUSB (controlled by PHY);
      * Enabling USB PHY passby in HCI mode (controlled by PMU).
      
      The current code will enable passby for each PHY and reroute PHY0 to
      MUSB, which is inconsistent and results in broken USB peripheral support.
      
      Passby on PHY0 must only be enabled when we want to use HCI. Since
      host/device mode detection is not available from the PHY code and
      because U-Boot does not support changing the mode dynamically anyway,
      we can just mux the controller to MUSB if it is enabled and mux it to
      HCI otherwise.
      
      This fixes USB peripheral support for platforms with PHY0 dual-route,
      especially H3/H5 and V3s.
      
      Signed-off-by: default avatarPaul Kocialkowski <paul.kocialkowski@bootlin.com>
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      0d5824cb
    • André Przywara's avatar
      arm: dts: sunxi: h3: Update DT files · 8fcf1fa2
      André Przywara authored
      
      Update the H3 DT files from the Linux 5.12 release.
      
      The changes update some boards, and don't affect U-Boot, but fix Gigabit
      Ethernet when this DT is passed on to the Linux kernel.
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      8fcf1fa2
    • André Przywara's avatar
      arm: dts: sunxi: h5: Update DT files · 58f68611
      André Przywara authored
      
      Update the H5 DT files from the Linux 5.12 release.
      
      The changes don't affect U-Boot at all, but fix Gigabit Ethernet when
      this DT is passed on to the Linux kernel. It also introduces DVFS.
      
      This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes
      that are of no concern to U-Boot.
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      58f68611
    • André Przywara's avatar
      arm: dts: sunxi: h6: Update DT files · 127e57c6
      André Przywara authored
      
      Update the H6 DT files from the Linux 5.12 release.
      
      The changes are minimal (many LED node renames), but also help to enable
      USB port 0 in U-Boot (later), enable the RSB device (not yet used in
      U-Boot), and also introduce an MMC frequency limit.
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      127e57c6
  2. Jul 08, 2021
  3. Jul 07, 2021
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