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  1. Aug 11, 2020
    • Suman Anna's avatar
      board: ti: am65x: Update fdt fixup logic for interconnect nodes · fc4c3802
      Suman Anna authored and Lokesh Vutla's avatar Lokesh Vutla committed
      
      The DT nodes on AM65x SoCs currently use a node name "interconnect" for
      the various interconnects. This name is not following the DT schema, and
      should simply be "bus". Update the fdt fixup logic to use both the
      current and the expected corrected path names so that this logic won't
      be broken with newer kernels.
      
      The logic also corrects the crypto node name as the DT node
      unit-addresses are all expected to be lower case.
      
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      fc4c3802
    • Faiz Abbas's avatar
      mmc: am654_sdhci: Use MMC_MODES_END value instead of hardcoded value · 7d6f45a2
      Faiz Abbas authored and Lokesh Vutla's avatar Lokesh Vutla committed
      
      The hardcoded array size leads to array overflows with changes in
      speed modes enum in mmc core. Use MMC_MODES_END for otap_del_sel
      array declaration to fix this.
      
      Signed-off-by: default avatarFaiz Abbas <faiz_abbas@ti.com>
      Reviewed-by: Peng Fan's avatarPeng Fan <peng.fan@nxp.com>
      7d6f45a2
    • Suman Anna's avatar
      arm: dts: k3-j721e: Fix interconnect node names · f3f2018f
      Suman Anna authored and Lokesh Vutla's avatar Lokesh Vutla committed
      
      The various CBASS interconnect nodes on K3 J721E SoCs are defined
      using the node name "interconnect". This is not a valid node name
      as per the dt-schema. Fix these node names to use the standard name
      used for SoC interconnects, "bus".
      
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      f3f2018f
    • Suman Anna's avatar
      arm: dts: k3-am65: Fix interconnect node names · 58edc6f6
      Suman Anna authored and Lokesh Vutla's avatar Lokesh Vutla committed
      
      The various CBASS interconnect nodes on K3 AM65x SoCs are defined
      using the node name "interconnect". This is not a valid node name
      as per the dt-schema. Fix these node names to use the standard name
      used for SoC interconnects, "bus".
      
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      58edc6f6
    • Derald D. Woods's avatar
      ARM: omap3: evm: Complete DM_ETH and DM_USB migrations · 5297a956
      Derald D. Woods authored and Lokesh Vutla's avatar Lokesh Vutla committed
      
      This commit completes the migrations for DM_ETH and DM_USB. The board
      is now consistent with omap3_beagle and other remaining OMAP3 boards.
      
      Cc: Tom Rini <trini@konsulko.com>
      Cc: Adam Ford <aford173@gmail.com>
      Signed-off-by: default avatarDerald D. Woods <woods.technical@gmail.com>
      5297a956
    • Andrew F. Davis's avatar
      arm: mach-k3: Clean non-coherent lines out of L3 cache · 864e2857
      Andrew F. Davis authored and Lokesh Vutla's avatar Lokesh Vutla committed
      
      When switching on or off the ARM caches some care must be taken to ensure
      existing cache line allocations are not left in an inconsistent state.
      An example of this is when cache lines are considered non-shared by
      and L3 controller even though the lines are shared. To prevent these
      and other issues all cache lines should be cleared before enabling
      or disabling a coherent master's cache. ARM cores and many L3 controllers
      provide a way to efficiently clean out all cache lines to allow for
      this, unfortunately there is no such easy way to do this on current K3
      MSMC based systems.
      
      We could explicitly clean out every valid external address tracked by
      MSMC (all of DRAM), or we could attempt to identify only the set of
      addresses accessed by a given boot stage and flush only those
      specifically. This patch attempts the latter. We start with cleaning the
      SPL load address. More addresses can be added here later as they are
      identified.
      
      Note that we perform a flush operation for both the flush and invalidate
      operations, this is not a typo. We do this to avoid the situation that
      some ARM cores will promote an invalidate to a clean+invalidate, but only
      emit the invalidation operation externally, leading to a loss of data.
      
      Signed-off-by: default avatarAndrew F. Davis <afd@ti.com>
      Tested-by: default avatarFaiz Abbas <faiz_abbas@ti.com>
      864e2857
    • Jan Kiszka's avatar
      arm: dts: k3: Add RTI watchdogs · e1c36685
      Jan Kiszka authored and Lokesh Vutla's avatar Lokesh Vutla committed
      Add DT entries for main domain watchdog0 and 1 instances on the J721e
      well as RTI1-based watchdog on the AM65x. RTI0 does not work for this
      purpose on the AM65x, so leave it out.
      
      On AM65x, we mark the power-domain as shared because RTI firmware such
      as https://github.com/siemens/k3-rti-wdt
      
       may request it as well in order
      to prevent accidental shutdown of the watchdog.
      
      Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
      e1c36685
    • Jan Kiszka's avatar
      watchdog: Add support for K3 RTI watchdog · d388f360
      Jan Kiszka authored and Lokesh Vutla's avatar Lokesh Vutla committed
      
      This is based on the Linux kernel driver for the RTI watchdog.
      
      To actually reset the system on an AM65x, it requires firmware running
      on the R5 that accepts the NMI and issues the actual system reset via
      TISCI. Kind of an iTCO, except that this watchdog hardware has support
      for no-way-out, and only for that.
      
      On the J721E, reset works without extra firmware help when routing the
      RTI interrupt via the ESM.
      
      Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
      d388f360
  2. Aug 10, 2020
  3. Aug 08, 2020
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