- Jul 29, 2021
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The PADCONFIG_202 register (0x02621328) is affected by the locking of the RSTMUX8 register (0x02620328), and so cannot be configured in kernel. This has been confirmed as a hardware bug and affects all K2G SoCs. Setup the pinmux for this pin before locking the RSTMUX8 register to allow the ICSS1 PRU1 Ethernet PHY port to work properly. The workaround was added only for the K2G-ICE board to configure the pins needed for the PRUSS Ethernet usecase. Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726232248.24395-1-s-anna@ti.com
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- Jul 27, 2021
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The J721E R5 SPL will no longer support booting of the Main R5FSS Core0 after the R5 SPL re-architecture for System Firmware split. The MCU R5F branch-only boot does not use the K3 R5F remoteproc driver, and relies only on the filesystem (FS) support for now. The K3 R5F remoteproc driver is therefore no longer needed in R5 SPL, so drop it from the J721E R5 defconfig. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-6-s-anna@ti.com -
The MAIN R5FSS0 cluster and corresponding nodes are no longer required to be enabled in R5 SPL after removing the support for booting any core from this cluster on R5 SPL. So, remove these from the relevant dts files. This is essentially a revert of the additions done in commit 2984b82b ("arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL"). Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-5-s-anna@ti.com -
The mach-k3 common code defined a weak start_non_linux_remote_cores() function so that the proper implementation can be plugged in the SoC-specific source files. This won't be needed anymore, so remove the the common code. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-4-s-anna@ti.com -
The common J7 specific start_non_linux_remote_cores() override function implements the logic to load and boot the Main R5FSS Core0 from R5 SPL. This won't be supported any more for either J721E or J7200 after the R5 SPL rearchitecture for the System Firmware split into TI Foundation Security (TIFS) and Device Management (DM) firmwares. So, cleanup the corresponding code and the related SPL env variables. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-3-s-anna@ti.com -
The Main R5FSS Core0 on J721E SoCs is originally booted from R5 SPL itself to achieve certain product-level early-boot metrics. This is no longer supported after the R5 SPL re-architecture (support merged for v2021.10-rc1). Move the booting of this core altogether from R5 SPL to A72 U-Boot. The env variables are left as is for now, and will be cleaned up in a subsequent patch. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-2-s-anna@ti.com -
The default U-Boot environment variables and design are all set up to have the MCU R5FSS cluster to be in Split-mode. This is the setting in v2021.01 U-Boot and the dt nodes are synched with the kernel binding property names in commit 468ec2f3 ("remoteproc: k3_r5: Sync to upstreamed kernel DT property names") merged in v2021.04-rc2. The mode for the cluster got switched back to LockStep mode by mistake in commit e4978763 ("arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-Boot") also in v2021.04-rc2. This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f@41400000: Invalid op: Trying to start secondary core 2 in lockstep mode Load Remote Processor 1 with data@addr=0x82000000 65268 bytes: Failed! Fix this by switching back the cluster to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes: e4978763 ("arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-Boot") Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726162213.28719-1-s-anna@ti.com -
Enable config to support gpt command on AM642 evm/sk and enable config for FDT library overlay support Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-7-a-govindraju@ti.com -
Enable configs to support eMMC boot. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-6-a-govindraju@ti.com -
configs: am64x_evm: Move CONFIG_SYS_MMC_ENV_DEV and CONFIG_SYS_MMC_ENV_PART to defconfig files and enable configs to save env in eMMC and FAT write. Kconfig symbols for SYS_MMC_ENV_DEV and SYS_MMC_ENV_PART have been added by commit 7d080773. Therefore, move the definitions of configs to corresponding board defconfig files and enable configs to save env in eMMC. Also enable config for FAT write in U-Boot. Fixes: 33b72589 ("board: ti: am64x: Add board support for am64x evm") Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-5-a-govindraju@ti.com -
Enable configs to support HS200/HS400. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-4-a-govindraju@ti.com -
arch: dts: am642-sk-u-boot: Disable main_sdhci0 DT node and define alias index 1 for main_sdhci1 node A Wilink wireless device is connected to MMCSD0 subsystem and is not supported in U-Boot. Therefore, disable main_sdhci0 device tree node in U-Boot. If main_sdhci0 device tree node is disabled then the the index of main_sdhci1 node becomes 0 which leads to break in boot flow. Therefore, add an alias to fix the index to 1. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-3-a-govindraju@ti.com -
Function spl_boot_mode() is called in common/spl/spl_mmc.c, to find the boot mode for a given boot device. This function was renamed to spl_mmc_boot_mode() by commit e9759065. Therefore, rename spl_boot_mode to spl_mmc_boot_mode. Fixes: 57dba04a ("arm: mach-k3: am642: Add support for boot device detection") Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-2-a-govindraju@ti.com -
CONFIG_SPL_TEXT_BASE was set to 0x70000000 in the commit, "26f32c32 configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy the limitations for USB DFU boot mode". This change seems to have been dropped during a merge commit. Therefore, fix this by setting CONFIG_SPL_TEXT_BASE to 0x70000000. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726145840.18977-1-a-govindraju@ti.com -
Add documentation for loading firmwares to be used by remote cores in the system including the environment variables that has to be set to load the firmwares. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-21-kishon@ti.com -
Move j721e document from board/ti/j721e/README to doc/board/ti/j721e_evm.rst after converting it to RST format. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-20-kishon@ti.com -
Add CONFIG_PREBOOT to provide an automatic and easier way to configure ethernet PHY before loading the firmware. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-19-kishon@ti.com -
MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1" on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 18. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: -
Add config for torrent serdes and common clock framework. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-17-kishon@ti.com -
Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra phy driver. All of them are required for USB3 support Signed-off-by:
Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-16-kishon@ti.com -
Add u-boot tags for torrent serdes. This has properties specific to u-boot on top of DT in v5.13 Linux Kernel. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-15-kishon@ti.com -
Add default lane function for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-14-kishon@ti.com -
Add DT node for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-13-kishon@ti.com -
Configure the parent clock of wiz3_pll0_refclk to the internal clock required for USB3 to be functional and also remove "ti,usb2-only" property as it now supports USB3 mode. This has properties specific to u-boot on top of DT present in v5.13 of Linux Kernel. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-12-kishon@ti.com -
Add support for probing and configuring Torrent serdes on J7200. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-11-kishon@ti.com -
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com -
Add driver for Torrent SERDES. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-9-kishon@ti.com -
Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by:
Alan Douglas <adouglas@cadence.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com -
AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-7-kishon@ti.com -
Add defines for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-6-kishon@ti.com -
Add defines for AM64 SERDES Wrapper. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-5-kishon@ti.com -
Add definitions for additional phy types that's used specifically for Torrent SERDES. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-4-kishon@ti.com -
Add test to check node name ignoring unit address. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20210721155849.20994-3-kishon@ti.com
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Add helper to compare node names. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: -
The SanCloud BeagleBone Enhanced (BBE) includes a Gigabit Ethernet PHY. Signed-off-by:Paul Barker <paul.barker@sancloud.com>
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This device tree is imported from Linux 5.13.1 and enabled via the am335x board file and the am335x evm defconfig. Signed-off-by: -
These device trees are updated to match the versions in Linux 5.13.1. The tick-timer entry in am335x-bone-common.dtsi is preserved. Signed-off-by: -
These headers are updated to match the versions in Linux 5.13.1. Signed-off-by: -
Enable configs to add support for HS400 speed mode. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210525093826.10390-4-a-govindraju@ti.com -
HS400 speed mode is now supported in J7200 SoC[1]. Therefore add mmc-hs400-1_8v tag in sdhci0 device tree node. Also update the delay values for various speed modes supported, based on the revised january 2021 J7200 datasheet[2]. [1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf, (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021) [2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf , (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021) Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210525093826.10390-3-a-govindraju@ti.com
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