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Patrick Delaunay's avatar
Patrick Delaunay authored
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.

This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

Without security, in basic boot, the value is equal to STM32_DDR_SIZE.

Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: default avatarPatrice Chotard <patrice.chotard@st.com>
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