- Feb 07, 2023
-
-
Drop this unused driver. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
Drop this unused driver. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
Drop this driver and the associated CONFIG option, as it is not used. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
This is not used anymore. Drop it. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Michael Trimarchi <michael@amarulasolutions.com>
-
This is not used in U-Boot. Drop it. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
- Feb 06, 2023
-
-
Add a bootdev device for qfw so that it can be used with standard boot. This simply checks for the correct method and then does the read. Most of the other logic is handed in a new bootmeth driver. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
At present virtio tries to attach QEMU services to a bootdev device, which cannot work. Add a check for this. Also use bootdev_setup_sibling_blk() to create the bootdev device, since it allows the correct name to be used and bootdev_get_sibling_blk() to work as expected. The bootdev is not created on sandbox since it does have a real virtio device and it is not possible to read blocks. Signed-off-by:
Simon Glass <sjg@chromium.org> Fixes: a60f7a3e ("bootstd: Add a virtio bootdev") Reported-by:
Ilias Apalodimas <ilias.apalodimas@linaro.org>
-
When QEMU does not respond for some reason, it is helpful to have debugging info to show. Add some. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
- Feb 04, 2023
-
-
Added tidss video driver support which enables display on oldi panel using AM62x, it creates a simple pipeline framebuffer==>vidl1==>ovr1==>vp1==>oldi_panel and calculates clock rates for panel from panel node in device tree. To compile TIDSS when user sets CONFIG_VIDEO_TIDSS add rule in Makefile. Include tidss folder location in Kconfig. TIDSS is ported from linux kernel version 5.10.145 Signed-off-by:
Nikhil M Jain <n-jain1@ti.com>
-
This patch updates the necessary Kconfigs to make simple panel driver independent of backlight driver and compiling backlight related code in simple-panel driver conditionally to when user has set CONFIG_BACKLIGHT. Signed-off-by:
Nikhil M Jain <n-jain1@ti.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
-
ofnode_decode_display_timing supports reading timing parameters from subnode of display-timings node, for displays supporting multiple resolution, in case if a display supports single resolution, it fails reading directly from display-timings node, to support it ofnode_decode_panel_timing is added. Signed-off-by:
Nikhil M Jain <n-jain1@ti.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
-
The commit 82f7b869 ("video: Drop CONFIG_AM335X_LCD") removed not only the LCD legacy implementation but also the code with driver model support. The patch restores the code with driver model support. Fixes: 82f7b869 ("video: Drop CONFIG_AM335X_LCD") Signed-off-by:
Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
-
- Feb 02, 2023
-
-
Prevent a NULL pointer dereference in the probe path by checking the return valud of dev_read_addr_ptr() against NULL. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
-
Remove the instances in which we have multiple blank lines. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
-
There were some cases in which the function parameters were not aligned to the open paranthesis. Fix those instances. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
-
Remove all the explicit casts from the void* returned by calloc. With this we also improve a bit the length of those lines and there is no need to split the assignment. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
-
The fsl-mc driver printed debug information which used the 0x prefix for decimal values. This only confuses anyone looking through the log. Because of this, just remove the prefix and use the "DPXY.<id>" notation which is the standard one for the DPAA2 objects. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
-
The break statement is just after a goto statement, thus it will not get executed. Just remove it. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
-
The cur_ptr variable is set to the start of the log buffer but then it's not used. Just remove the assignment altogether. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
-
Add a DSA driver for the MV88E6xxx compatible Ethernet switches. Cc: Marek Behún <marek.behun@nic.cz> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Reviewed-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by:
Fabio Estevam <festevam@denx.de>
-
Add support for DM_MDIO by registering a UCLASS_MDIO driver and attempting to use it. This is necessary if wanting to use a DSA driver for example hanging off of the FEC MAC. Care is taken to fallback to non DM_MDIO mii bus as several boards define DM_MDIO without having the proper device-tree configuration necessary such as an mdio subnode, a phy-mode prop, and either a valid phy-handle prop or fixed-phy subnode which will cause dm_eth_phy_connect() to fail. Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Reviewed-by:
Fabio Estevam <festevam@denx.de>
-
Remove the unnecessary xmit and recv functions. Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Reviewed-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by:
Fabio Estevam <festevam@denx.de>
-
Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by:
Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by:
Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by:
Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom <twarren@nvidia.com>
-
Enum clock_osc_freq was designed to use only with T20. This patch remaps it to use additional frequencies, added in T30+ SoC while maintaining backwards compatibility with T20. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by:
Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom <twarren@nvidia.com>
-
Marek Vasut authored
The current set of U-Boot upstream R-Car Gen3 DTs all contain generic "renesas,etheravb-rcar-gen3" compatible strings, drop the SoC specific compatible string support from U-Boot to reduce size and duplication. Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
-
Hai Pham authored
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but similar enough to reuse code. Introduce a new CPG library, factor out the SD clock and RPC clock handling and hook them to the generic Gen3 CPG driver so we have an equal state. Based on Linux commit [1] and [2] by Wolfram Sang [1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library") [2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to the library") Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Add rcar_clk_* prefix to all functions - Rebase on changes to clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function - Use u32_encode_bits/GENMASK bitfield ops
-
Hai Pham authored
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. Hence, new clock types are introduced respectively. Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead - Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types which is now part of common clock types in rcar-gen3-cpg.h instead
-
Hai Pham authored
The old SD handling code was huge and could not handle all the details which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to another design. Have SDnH a separate clock, use the existing divider clocks and move the errata handling from the clock driver to the SDHI driver where it belongs. Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") and commit e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH") Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Add rcar_clk_* prefix to all functions - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead - Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and rate = 200000000, the divider would be 0 and table lookup would fail. - Turn rcar_clk_get_table_val into signed integer, so it can return 0 as a valid value and negative values as errors. - Make the code operate on correct clock and add comment which explains the reasoning behind it. - Rebase on changes to clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
-
Hai Pham authored
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car E3, but uses a different pre-divider for the PLL0 parent. Add a new macro to describe it, reusing the existing clock type for R-Car E3. As both E3/D3 RPCSRC clock divider are different from the rest of R-Car Gen3, keep the original implementation from Linux. Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add RPC clocks") by Geert Uytterhoeven. Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Add D3 tweaks
-
Hai Pham authored
Introduce new helper function to handle clock type that uses clk_div_table struct. Based vaguely on Linux code. Make use of clk_div_table in RPC clocks handling. The E3/D3 RPCSRC need to be handled differently and will be addressed in subsequence patch. Based on Linux commit db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") by Sergei Shtylyov. Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Squash patches to avoid adding unused code: clk: renesas: Make use of clk_div_table in RPC clocks handling clk: renesas: Introduce rcar_clk_get_rate64_div_table function - Move the new code to the beginning of clk-rcar-gen3 to avoid tables mixed with code - Use rcar_ prefix for get_table_div function - Get rid of custom macros, use GENMASK. Use custom field_get implementation as the generic FIELD_GET does not support constant mask and u32_get_bits requires higher optimization level - Pass in the register bit mask instead of width/shift combination - Turn rcar_clk_get_rate64_div_table into s64, as it can return -EINVAL
-
Marek Vasut authored
Replace custom local structure with matching one from clk-provider.h . No functional change. Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
-
Hai Pham authored
V3M handles SDnH differently than other Gen3 SoCs, so let's add a separate entry for that. This will allow better SDnH handling in the future. Based on Linux commit 627151b4966f ("mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M") by Wolfram Sang Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
-
Hai Pham authored
It is unnecessary, so clean it up. Reviewed-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message, mention ES3.0 Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
-
Hai Pham authored
Support R8A77961 M3-W+ SoC. Reviewed-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
-
Hai Pham authored
Still uses 0x3 for now, adjust the offset value to TMPPORT3 accordingly Reviewed-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
-
Hai Pham authored
Adjust HS400 calibration tables based on Linux settings Reviewed-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
-
Hai Pham authored
Further filter out HS400 support on certain SoCs. Since M3-W r1.2 does not support HS400, drop the calibration table and rename the one for M3-W r1.3 to r8a7796_rev13_calib_table Reviewed-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
-
Hai Pham authored
Early ES revisions of M3-W SoCs requires 4-tap HS400. Reflect the status from datasheet. Reviewed-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
-
Marek Vasut authored
Drop 'core' parameter from gen3_clk_get_rate64_pll_mul_reg() function as it is only used in debug print. No functional change except for the debug print, which is disabled by default. Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
-
Hai Pham authored
Since commit f7b4e4c0 ("clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12"), the custom macros for RPC clocks were dropped. Use pre-defined offset for RPC clocks, same as what Linux does, instead of retrieving it from the macros Reviewed-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
-