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  • Lukasz Majewski Lukasz Majewski lukma
  • Mattijs Korpershoek Mattijs Korpershoek mkorpershoek
  • Tom Rini Tom Rini trini
3 authors
  1. Sep 15, 2022
  3. Sep 13, 2022
    • Stefan Roese's avatar
      cyclic: Add 'cyclic list' and 'cyclic demo' commands · 1f865ee0
      Stefan Roese authored and Tom Rini's avatar Tom Rini committed 
      
This patch adds the cyclic command, which currently only supports the
'list' subcommand, to list all currently registered cyclic functions.
Here an example:

=> cyclic list
function: cyclic_demo, cpu-time: 7010 us, frequency: 99.80 times/s
function: cyclic_demo2, cpu-time: 1 us, frequency: 1.13 times/s

As you can see, the cpu-time is accounted, so that cyclic functions
that take too long might be discovered. Additionally the frequency is
logged.

The 'cyclic demo' commands registers the cyclic_demo() function to
be executed all 'cycletime_ms' milliseconds. The only thing this
function does is delaying by 'delay_us' microseconds.

Signed-off-by: default avatarStefan Roese <sr@denx.de>
Reviewed-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      1f865ee0
    • Stefan Roese's avatar
      cyclic: Add basic support for cyclic function execution infrastruture · c2c69718
      Stefan Roese authored and Tom Rini's avatar Tom Rini committed 
      
Add the basic infrastructure to periodically execute code, e.g. all
100ms. Examples for such functions might be LED blinking etc. The
functions that are hooked into this cyclic list should be small timewise
as otherwise the execution of the other code that relies on a high
frequent polling (e.g. UART rx char ready check) might be delayed too
much. This patch also adds the Kconfig option
CONFIG_CYCLIC_MAX_CPU_TIME_US, which configures the max allowed time
for such a cyclic function. If it's execution time exceeds this time,
this cyclic function will get removed from the cyclic list.

How is this cyclic functionality executed?
The following patch integrates the main function responsible for
calling all registered cyclic functions cyclic_run() into the
common WATCHDOG_RESET macro. This guarantees that cyclic_run() is
executed very often, which is necessary for the cyclic functions to
get scheduled and executed at their configured periods.

This cyclic infrastructure will be used by a board specific function on
the NIC23 MIPS Octeon board, which needs to check periodically, if a
PCIe FLR has occurred.

Signed-off-by: default avatarStefan Roese <sr@denx.de>
Reviewed-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      c2c69718
    • Chin-Ting Kuo's avatar
      spi: aspeed: Add ASPEED SPI controller driver · 4daa6bb6
      Chin-Ting Kuo authored and Tom Rini's avatar Tom Rini committed 
      
Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.

There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
       fetches initial device boot image from FMC chip select(CS) 0.

- SPI1: Play the role of a SPI Master controller. Or, there is a
        dedicated path for HOST(X86) to access its BIOS flash mounted
        under BMC. spi-aspeed-smc.c implements the control sequence when
        SPI1 is a SPI master.

- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
        mounted under it are for pure storage purpose.

ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
               13h is used to fetch boot image from SPI flash.
               - AST2500: Only 03h command can be used after power on
                          or reset.
               - AST2600: If FMC04[6:4] is set, 13h command is used,
                          otherwise, 03h command.
               The address length is decided by FMC04[2:0].

- Command mode: SPI controller can send command and address
                automatically when CPU read/write the related remapped
                or decoded address area. The command used by this mode
                can be configured by FMC10/14/18[23:16]. Also, the
                address length is decided by FMC04[2:0]. This mode will
                be implemented in the following patch series.

- User mode: It is a traditional and pure SPI operation, where
             SPI transmission is controlled by CPU. It is the main
             mode in this patch.

Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.

This patch only implements user mode initially. Command read/write
mode will be implemented in the following patches.

Signed-off-by: default avatarChin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
      4daa6bb6
  5. Aug 20, 2022
  7. Aug 16, 2022
  9. Aug 10, 2022
  11. Aug 01, 2022
    • Marek Behún's avatar
      MAINTAINERS: Change POWERPC MPC85XX maintainer to Marek Behún · 707b17f6
      Marek Behún authored and Tom Rini's avatar Tom Rini committed 
      
After a discussion with Tom Rini, we've agreed that I am going to take
over custodianship of the MPC85XX platform, since it seems other people
do not have necessary interest or time and getting things done over
there takes too long.

Since I am only working on one MPC85XX board, Turris 1.x, and do not
have time to do thorough reviews of patches for this entire platform
(other than those concerning Turris 1.x board), for other boards I will
only run patches through CI and checkpatch, and then send them via PR
upwards to Tom.

Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Acked-by: default avatarTom Rini <trini@konsulko.com>
      707b17f6
  13. Jul 26, 2022
    • Martyn Welch's avatar
      MAINTAINERS: Update file list for ARM Freescale IMX · bb19f851
      Martyn Welch authored and Stefano Babic's avatar Stefano Babic committed 
      
The MAINTAINERS file currently lists files in
arch/arm/include/asm/arch-imx/ being part of the IMX maintainers
purview, however the arch/arm/include/asm/ directory also contains the
directories arch-imx8, arch-imx8m, arch-imx8ulp and arch-imxrt which
would also appear to be relevant to the team. Tweak the entry to cover
these directories so that tools like get_maintainers.pl will suggest
relevant maintainers when making changes just in these directories.

Signed-off-by: default avatarMartyn Welch <martyn.welch@collabora.com>
      bb19f851
  15. Jul 25, 2022
  17. Jul 21, 2022
  19. Jul 13, 2022
  21. Jul 07, 2022
  23. Jul 01, 2022
  25. Jun 29, 2022
  27. Jun 24, 2022
  29. Jun 23, 2022
  31. Jun 20, 2022
    • Sean Anderson's avatar
      arm: layerscape: Add sfp driver · 2645bc0e
      Sean Anderson authored and Peng Fan's avatar Peng Fan committed 
      
This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.

The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.

The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.

I suggest using the following procedure for programming:

1. Override the fuses you wish to program
   => fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
   => fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
   write-protect bit you will usually want to write it last anyway.
   => fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
   => fuse read 0 2 4

Signed-off-by: default avatarSean Anderson <sean.anderson@seco.com>
      2645bc0e
  33. Jun 17, 2022
  35. Jun 10, 2022
  37. Jun 08, 2022
    • Sean Anderson's avatar
      misc: Add support for nvmem cells · c8ce7ba8
      Sean Anderson authored and Tom Rini's avatar Tom Rini committed 
      
This adds support for "nvmem cells" as seen in Linux. The nvmem device
class in Linux is used for various assorted ROMs and EEPROMs. In this
sense, it is similar to UCLASS_MISC, but also includes
UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding
to a Linux-style nvmem device should be implemented as one of the
previously-mentioned uclasses. The nvmem API acts as a compatibility
layer to adapt the (slightly different) APIs of these uclasses. It also
handles the lookup of nvmem cells.

While nvmem devices can be accessed directly, they are most often used
by reading/writing contiguous values called "cells". Cells typically
hold information like calibration, versions, or configuration (such as
mac addresses).

nvmem devices can specify "cells" in their device tree:

	qfprom: eeprom@700000 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x00700000 0x100000>;

		/* ... */

		tsens_calibration: calib@404 {
			reg = <0x404 0x10>;
		};
	};

which can then be referenced like:

	tsens {
		/* ... */
		nvmem-cells = <&tsens_calibration>;
		nvmem-cell-names = "calibration";
	};

The tsens driver could then read the calibration value like:

	struct nvmem_cell cal_cell;
	u8 cal[16];
	nvmem_cell_get_by_name(dev, "calibration", &cal_cell);
	nvmem_cell_read(&cal_cell, cal, sizeof(cal));

Because nvmem devices are not all of the same uclass, supported uclasses
must register a nvmem_interface struct. This allows CONFIG_NVMEM to be
enabled without depending on specific uclasses. At the moment,
nvmem_interface is very bare-bones, and assumes that no initialization
is necessary. However, this could be amended in the future.

Although I2C_EEPROM and MISC are quite similar (and could likely be
unified), they present different read/write function signatures. To
abstract over this, NVMEM uses the same read/write signature as Linux.
In particular, short read/writes are not allowed, which is allowed by
MISC.

The functionality implemented by nvmem cells is very similar to that
provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does
not seem to have made its way into Linux or into any device tree other
than sandbox. It is possible that with the introduction of this API it
would be possible to remove it.

Signed-off-by: default avatarSean Anderson <sean.anderson@seco.com>
      c8ce7ba8
  39. May 26, 2022
  41. Apr 25, 2022

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