Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

At present sandbox builds package up u-boot.bin in the .img file. This
cannot actually be executed, since it is not an ELF file.

For sandbox_vpl we want to be able to run the full boot flow.

Adjust the build rule for sandbox_vpl to package the ELF file and
thereby allow full testing of the sandbox transition from SPL to U-Boot
proper.

Signed-off-by: Simon Glass <sjg@chromium.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

The existing API for these functions is different from the rest of
U-Boot, in that any error code must be obtained from the errno variable
on failure. This variable is part of the C library, so accessing it
outside of the special 'sandbox' shim-functions is not ideal.

Adjust the API to return an error code, to avoid this. Update existing
uses to check for any negative value, rather than just -1.

Signed-off-by: Simon Glass <sjg@chromium.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

Since the removal of OF_HOSTFILE logic in board_fdt_blob_setup(), the
logic for obtaining the DT is handled in the OF_BOARD option. If a
devicetree comes from a bloblist it is immediately overwritten by this
function.

Fix this by skipping the function if a devicetree is already present.

This is sort-of a fix for e7fb7896 ("sandbox: Remove OF_HOSTFILE") but
it has only come to light since bloblist was added, so I have not added
a Fixes tag.

Unfortunately it is not possible to report the correct FDT source with
the current code. It might be best to use an error-return code for
board_fdt_blob_setup() so that an error can be reported if the board
does not provide the DT.

Signed-off-by: Simon Glass <sjg@chromium.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

When the devicetree comes from a bloblist, it is currently overwritten
by the appended one, if present. It should be preserved.

Adjust the logic to support this.

Fixes: 70fe2385 ("fdt: Allow the devicetree to come from a bloblist")

Signed-off-by: Simon Glass <sjg@chromium.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

This code is useful for loading an image in sandbox_spl so move it into
a place where it can be called as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

Fix a missing dot in a comment, since '..' is confusing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

The argument array is not changed by the callee, so mark it const.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>

Signed-off-by: Tom Rini <trini@konsulko.com>

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>

Simon Glass <sjg@chromium.org> says:

This series includes fixes to get some rockchip and nvidia boards
working again. It also drops the broken Beaglebone Black config and
provides a devicetree fix for coral (x86).

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

The code here is confusing due to large blocks which are #ifdefed out.
Add a function phase_sdram_init() which returns whether SDRAM init
should happen in the current phase, using that as needed to control the
code flow.

This increases code size by about 500 bytes in SPL when the cache is on,
since it must call the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass <sjg@chromium.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

At present gd->ram_size is 0 in SPL, meaning that it is not possible to
enable the cache. Correct this by always populating the RAM size
correctly.

This increases code size by about 500 bytes in SPL, since it must call
the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

On some boards, the bloblist is created in SPL once SDRAM is ready. It
cannot be accessed until that point, so is not available early in SPL.

Add a condition to avoid a hang in this case.

This fixes a hang in chromebook_coral

Fixes: 70fe2385 ("fdt: Allow the devicetree to come from a bloblist")

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Raymond Mao <raymond.mao@linaro.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

There is no need to remove input files. It makes it harder to diagnose
failures. Keep the payload file.

There is no test for this condition, but one could be added.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

The tool must return an error code when invalid arguments are provided,
otherwise binman has no way of knowing that anything went wrong.

Correct this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: fab430be ("tools: add mkeficapsule command for UEFI...")

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

Tools cannot be assumed to be present. Add a check for this with the
mkeficpasule tool.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: b617611b ("binman: capsule: Add support for generating...")

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

Now that this tool has a version number, collect it.

Signed-off-by: Simon Glass <sjg@chromium.org>

Simon Glass authored 7 months ago and Tom Rini committed 7 months ago

Tools should have an option to obtain the version, so add this to the
mkeficapsule tool.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21846

- Convert warp7 to OF_UPSTREAM.
- Add 'cpu' command to imx8m and imx93.
- Enable CMD_ERASEENV for imx8mm/mp Phytec boards.

This change adds support for PCIe connected nvme disk - phyBOARD-Polis
base board.

One needs to call following commands in u-boot:
> pci enum
> nvme scan
> nvme info

And then ones to access proper file system (like fat[ls|load|write],
ext4[ls|load|write]).

Signed-off-by: Lukasz Majewski <lukma@denx.de>

Enable the 'cpu' command to display the CPU info and release CPU core to
run baremetal or RTOS applications.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Enable the 'cpu' command and the depended imx CPU driver to
display the CPU info and release CPU core to run baremetal
or RTOS applications.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Added the original author Simon and myself.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus
as a example.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Add a new subcommand 'release' to bring up a core to run baremetal
and RTOS applications.

For example on i.MX8M Plus EVK, release the LAST core to run a RTOS
application, passing the sequence number of the CPU core to release,
here it is 3:
    u-boot=> cpu list
      0: cpu@0      NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
      1: cpu@1      NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C
      2: cpu@2      NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
      3: cpu@3      NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C

    u-boot=> load mmc 1:2 c0000000 /hello_world.bin
    66008 bytes read in 5 ms (12.6 MiB/s)
    u-boot=> dcache flush; icache flush
    u-boot=> cpu release 3 c0000000
    Released CPU core (mpidr: 0x3) to address 0xc0000000

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Release the secondary cores through the PSCI request.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Add i.MX 8M Mini, Nano and Plus SoCs support.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Return CPU description string without newline character in the end.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Increase one more bit to cover all CPU types. Otherwise it shows
wrong CPU info on some platforms, such as i.MX8M Plus:

    U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +0000)

    CPU:   NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C

    Model: NXP i.MX8MPlus LPDDR4 EVK board

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The cpu_freq stores the current CPU frequency in Hz.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>

Add test for API cpu_release_core().

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Add empty release CPU core function for testing.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Add a new callback release_core to the cpu_ops, which is used to
release a CPU core to run baremetal or RTOS application on a SoC
with multiple CPU cores.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing
for enabling the 'cpu' command, which depends on this to print CPU core
frequency.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Enable erasing environment with eraseenv command.

Signed-off-by: Yannic Moog <y.moog@phytec.de>

Enable erasing environment with eraseenv command.

Signed-off-by: Yannic Moog <y.moog@phytec.de>

Enable erasing environment with eraseenv command.

Signed-off-by: Yannic Moog <y.moog@phytec.de>

Instead of using the local imx7s-warp devicetree copies from U-Boot,
convert the imx7s-warp board to OF_UPSTREAM so that the upstream
kernel devicetree can be used instead.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Michael Trimarchi authored 8 months ago and Tom Rini committed 7 months ago

Print clk name in clk_enable and clk_disable. Make sense to know
what clock get disabled/enabled before a system crash or system
hang.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

Alexander Dahl authored 10 months ago and Tom Rini committed 7 months ago

The function returns the rate of the parent clock, the previous text
made no sense at all.

Fixes: 4aa78300 ("dm: clk: Define clk_get_parent_rate() for clk operations")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>