Bin Meng authored 9 years ago and Tom Rini committed 9 years ago

When trying to access non-existent/unsupported PCI devices in
imx_pcie_read_config(), when imx_pcie_addr_valid() fails it returns
error code and fills in the result with 0xffffffff manually. But it
really should return zero to upper layer codes.

Reported-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

Michal Simek authored 9 years ago and Tom Rini committed 9 years ago

Mark _debug_uart_init() as static to avoid sparse warning and
inline it to debug_uart_init().

Reported-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Robert P. J. Day authored 9 years ago and Tom Rini committed 9 years ago

Correct mismatched comment on #endif to agree with its #if defined().

Also add some missing #endif comments for consistency, take out
extraneous blank lines for readability.

rday

Joe Hershberger authored 9 years ago and Simon Glass committed 9 years ago

Introduced in 45b47734 (net/arp: account for ARP delay, avoid duplicate packets on timeout)

Check the arp timeout and adjust the timeout start time before the call
to eth_recv() so that the sandbox driver has the opportunity to adjust
the sandbox timer after the new start time has been recorded.

Also, change the adjustment amount by 11 seconds instead of exactly the
10 seconds that the ping timout is expecting since the timeout check is
looking for the time elapsed to be greater than but not equal to the
specified delay.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Simon Glass <sjg@chromium.org>

This commit fixes the change of below commit
"spi: fsl_qspi: Use GENMASK"
(sha1 :bad490a2)

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

stm_is_locked_sr() takes the status register (SR) value as the last
parameter, not the second.

Based on a patch from Brian Norris for the linux kernel:
http://git.infradead.org/linux-mtd.git/commit/a32d5b726ff8cf32bf491522b0ac8ae2545a063e



Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

Miao Yan authored 9 years ago and Tom Rini committed 9 years ago

In struct e1000_rx_desc, field 'length' is declared as
uint16_t, so use le16_to_cpu() to do endianness conversion.

Also drop conversion on 'status' which is declared as
uint8_t.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Eric Nelson authored 9 years ago and Tom Rini committed 9 years ago

Table 41 of the JEDEC standard for eMMC says that bit 31 of
the command argument is obsolete when issuing the ERASE
command (CMD38) on page 115 of this document:
	http://www.jedec.org/sites/default/files/docs/jesd84-B45.pdf

The SD Card Association Physical Layer Simplified Specification also
makes no mention of the use of bit 31.
	https://www.sdcard.org/downloads/pls/part1_410.pdf



The Linux kernel distinguishes between secure (bit 31 set) and
non-secure erase, and this patch copies the macro names from
include/linux/mmc/core.h.

Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Eric Nelson <eric@nelint.com>
Tested-by: Hector Palacios <hector.palacios@digi.com>

Ladislav Michl authored 9 years ago and Heiko Schocher committed 9 years ago

drivers/mtd/ubi/io.c:1354:3: error: 'dump_len' undeclared (first use in
this function)
   dump_len = max_t(int, 128, len - i);

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

Gong Qianyu authored 9 years ago and Stefano Babic committed 9 years ago

This could avoid executing the code that only applies to i.MX platforms.

The bus_i2c_init() is called before relocation and will assgin value
to a static variable. If U-Boot is then still running in a flash
device, it's theoretically not allowed to write data to flash without
an erasing operation. For i.MX platforms, the U-Boot is always running
in DDR.

Actually it causes asynchronous error when the ARM64 system error
report is enabled and the flash write protect is set.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

Måns Rullgård authored 9 years ago and Stefano Babic committed 9 years ago

If fecmxc_initialize_multi() fails, it frees but does not unregister
the mdio bus, causing subsequent uses of the "mii" command to crash.
Fix this by adding mdio_unregister() calls where needed.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Reviewed-by: Eric Nelson <eric@nelint.com>

Måns Rullgård authored 9 years ago and Stefano Babic committed 9 years ago

If the host clock frequency is higher than 100 MHz, the MDIO hold
time needs to be increased from its current setting of one cycle in
order to meet the specified minium of 10 ns.  Writing an appropriate
value to the HOLDTIME field of the MII_SPEED register achieves this.

Comment copied from Linux kernel.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Reviewed-by: Eric Nelson <eric@nelint.com>

Maximilian Schwerin authored 9 years ago and Stefano Babic committed 9 years ago

This patch writes the default values for TXTL and RXTL to UARTx_UFCR.
Without this patch some older kernel versions crash as UARTx_UFCR was
not always correctly initialized.

Signed-off-by: Maximilian Schwerin <maximilian.schwerin@tigris.de>

Eric Nelson authored 9 years ago and Stefano Babic committed 9 years ago

The low four bits of the SYSCTL register are reserved on the USDHC
controller on i.MX6 and i.MX7 processors, but are used for clocking
operations on earlier models.

Guard against their usage by hiding the bit mask macros on those
processors.

These bits are used to prevent glitches when changing clocks on
i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7.

>From the i.MX6DQ RM:
	To prevent possible glitch on the card clock, clear the
	FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS
	or DVS in System Control Register) or setting RSTA bit.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Hector Palacios <hector.palacios@digi.com>

Stefan Brüns authored 9 years ago and Marek Vasut committed 9 years ago

The ifdef'ed Linux kernel code uses the 1 based port number, whereas U-Boot
puts a 0 based port number into the register. The reason the 0 based port
number apparently works can probably be taken from the USB 2.0 spec:

8.4.2.2 Start-Split Transaction Token
... The host must correctly set the port field for single and multiple TT
hub implementations. A single TT hub implementation *may ignore* the port
field.

Actually, as far as I understand, a multi TT hub defaults to single TT
(bAlternateSetting: 0) until switched via SetInterface, so even "port 42"
would work.

The change was verified by hardcoding the port number to a wrong value,
SPLIT transactions kept working (although using a DWC2 instead of MUSB).
Tested hubs are the RPi onboard SMC9514 and an external "05e3:0608
Genesys Logic, Inc. USB-2.0 4-Port HUB". The former is a multi TT hub,
the latter single TT only.

Addendum: Tested on sunxi/MUSB by Hans de Goede

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>

Stefan Brüns authored 9 years ago and Marek Vasut committed 9 years ago

Start split and complete split tokens need the hub address and the
downstream port of the first HS hub (device view).

The core of the function was duplicated in both host/ehci_hcd and
musb-new/usb-compat.h.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>

Stefan Brüns authored 9 years ago and Marek Vasut committed 9 years ago

flush_dcache_range may access data after priv->aligned_buffer end if
len > DWC2_DATA_BUF_SIZE.
memcpy may access data after buffer end if done > 0

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Allow ctrl-c to abort the erase ops.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

Show sector erase progress with dot and comma.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

Skip erase if the sector is blank. The sector erase is slow, and
may take 0.7 sec typically or up to 3 sec worst-case.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

If the erase fails, fail_addr might indicate exactly which block
failed. If fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not
at the device level or was not specific to any particular block.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

Erase is an asynchronous operation.  Device drivers are supposed
to call instr->callback() whenever the operation completes, even
if it completes with a failure.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

Trailing backslashes are necessary only in macros, not in the actual
code, so remove them.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>

Thomas Chou authored 9 years ago and Marek Vasut committed 9 years ago

Select PHYLIB in drivers/net/Kconfig. And remove CONFIG_PHYLIB
from legacy board header files.

This fixed the warnings when both ALTERA_TSE and ETH_DESIGNWARE
are selected.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reported-by: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Dinh Nguyen authored 9 years ago and Marek Vasut committed 9 years ago

Move the macro into the socfpga_dwmci_clksel().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
[fix parenthesis in the sdmmc_mask]

Add code to process the KSZ9021/KSZ9031 OF props if they are present
and configure skew registers based on the information from the OF.
This code is only enabled if the DM support for ethernet is also
enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

V2: - Implement struct ksz90x1_reg_field to describe the skew register
      fields more accurately.
    - Fix RXDV/TXEN skew register default value and offset.

Initialize instr.mtd in flash_erase(). This fixes the system
hang issue when CONFIG_MTD_PARTITIONS is selected.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>

Clear driver dependecies via Kconfig. Remove PHYLIB dependency from
the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Use core to call net_process_received_packet() instead of call inside
the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

recv function should return 0 instead of frame_len not to
proceed the same packet again in core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Undefined phy address is -1 not 0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

When the Zynq Boot ROM code loads the payload from QSPI it uses the
LQSPI feature of the QSPI device, however it does not clean up its
configuration before handing over to the payload which leaves the device
confgured to by-pass the standard non-linear operating mode.

This ensures the Linear QSPI mode is disabled before re-enabling the
device.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Alexey Brodkin authored 9 years ago and Marek Vasut committed 9 years ago

This driver is meant to be used with any OHCI-compatible host
controller in case if there's no need for platform-specific
glue such as setup of controller or PHY's power mode via
GPIOs etc.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>

Łukasz Majewski authored 9 years ago and Marek Vasut committed 9 years ago

With the old order of initialization the hcor pointer has been setup to
the same address as Exynos EHCI base address (0x12110000 instead of
0x12110010).
Such behaviour was caused by reading value of 0 instead of 0x10 from EHCI
HCCPBASE register without doing proper clock initialization before.

To fix this problem hcor initialization has been moved after USB PHY setup.
Now ehci_readl(&ctx->hcd->cr_capbase) returns correct value.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>

The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.

The rename is done automatically:
	$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
		`git grep "s3c_udc\.h" | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.

The rename is done automatically:
	$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
		`git grep s3c_udc_probe | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.

The rename is done automatically:
	$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
		`git grep s3c_plat_otg_data | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>

The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the
config option to make it less misleading. No functional change, just
a mechanical change done using the following script:

  git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \
  while read line ; do
    sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ;
  done

Signed-off-by: Marek Vasut <marex@denx.de>

The driver is actually for the Designware DWC2 controller.
Tweak the comments in the driver to reflect this fact.

Signed-off-by: Marek Vasut <marex@denx.de>