- Mar 26, 2024
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Pull the PHY GPIO reset code into separate function, since this is and will be reused multiple times. Set up default reset assert and deassert timing to generous 20ms and 1ms for maximum compatibility in case those DT properties are missing. Reviewed-by:
Ramon Fried <rfried.dev@gmail.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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This patch adds support for i225-IT in e1000 driver. Add e1000_phy_igc. Signed-off-by:Marjolaine Amate <marjolaine.amate@odyssee-systemes.fr>
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From the ethernet header is not on aligned, because the length of the ethernet header is 14 bytes. Therefore, unaligned access must be done here. Signed-off-by:Jacky Chou <jacky_chou@aspeedtech.com>
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There is no need to perform the endian twice here. Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org>
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They are not required to be global, make them static. Signed-off-by:Yang Xiwen <forbidden405@outlook.com>
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3 operations needed by `net stats` are implemented. New `net stats` output some useful info. Signed-off-by: -
register internal MDIO bus device if it is a subnode. Signed-off-by: -
shrink the first argument of log_msg_ret(), add dev_xxx() functions for error reporting. Fixes: 9d8f78a2 ("net: add hifemac Ethernet driver for HiSilicon platform") Signed-off-by:
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The initial commit used log_msg_ret() wrongly. Fix that by moving error report to a separate dev_err() call and shrink the first argument of log_msg_ret() to no more than 4 chars. Fixes: 6b5c8d98 ("net: add hifemac_mdio MDIO bus driver for HiSilicon platform") Signed-off-by:
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As with fixed-link phy device, the NC-SI phy devive does not require an mdio bus. So, a condition is added to check the NC-SI phy id to avoid accessing the bus pointer that is NULL. Signed-off-by: -
Booting R-Car Gen3 arm64 U-Boot with CONFIG_UBSAN=y resulted in: ===================================================================== UBSAN: Undefined behaviour in drivers/net/phy/phy.c:728:19 left shift of 1 by 31 places cannot be represented in type 'int' ===================================================================== Fix it by appending the UL suffix to the numeric literal. While at it, convert the type of "addr" variable from signed to unsigned, to protect against shifting the numeric literal by a negative value (which would lead to yet another undefined behavior). Fixes: 1adb406b ("phy: add phy_find_by_mask/phy_connect_dev") Signed-off-by:
Eugeniu Rosca <erosca@de.adit-jv.com> * Using U-suffix for integer is sufficient. * ffs() of non-zero value cannot be 0. But addr being unsigned is * preferable. Signed-off-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Configure LEDs on BCM54210E so they would blink on activity and indicate link speed. Without this the LEDs are always on if cable is plugged in. Signed-off-by:Marek Vasut <marex@denx.de>
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The issue occurs the UAF (use-after-free) to cause double free when do the realloc function for the pointers during the reinitialization NC-SI process, and it will cause the memory management occurs error. So, nullify these pointers after free. Signed-off-by:
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- Mar 24, 2024
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Mathieu Othacehe authored
This message is used to commit into the fuses any new SRK revocation and FW version information that have been found into the NXP (ELE FW) and OEM containers. Signed-off-by:Mathieu Othacehe <othacehe@gnu.org>
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Sumit Garg authored
Since now we have the modern pcie_dw_imx.c driver for iMX SoCs, encourage people to switch to that for any further new iMX SoC support or even for the older iMX6 SoCs too. Suggested-by:
Peter Robinson <pbrobinson@gmail.com> Signed-off-by:
Sumit Garg <sumit.garg@linaro.org> Reviewed-by:
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Sumit Garg authored
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is tied to quite old port of pcie_designware driver from Linux which suffices only iMX6 specific needs. But currently we have the common DWC specific bits which alligns pretty well with DW PCIe controller on iMX8MP SoC. So lets reuse those common bits instead as a new driver for iMX8 SoCs. It should be fairly easy to add support for other iMX8 variants to this driver. iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we can reuse the generic PHY infrastructure to power on PCIe PHY. Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by:
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Sumit Garg authored
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe PHY initialization moved to this standalone PHY driver. Inspired from counterpart Linux kernel v6.8-rc3 driver: drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver reference commit 7559e7572c03 ("phy: Explicitly include correct DT includes"). Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by: -
Sumit Garg authored
Expose the high performance PLL as clock framework clock, so the PCIe PHY can use it when there is no external refclock provided. Inspired from counterpart Linux kernel v6.8-rc3 driver: drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to platform remove callback returning void"). Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by: -
Sumit Garg authored
Add support for GPCv2 power domains and clock handling for PCIe and PCIe PHY. Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by:
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Sumit Garg authored
Add support for i.MX8MP reset controller, it has same reset IP inside as the other iMX7 and iMX8M variants but with different module layout. Inspired from counterpart Linux kernel v6.8-rc3 driver: drivers/reset/reset-imx7.c. Use last Linux kernel driver reference commit bad8a8afe19f ("reset: Explicitly include correct DT includes"). Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by: -
Sumit Garg authored
imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared with imx*_reset_{deassert/assert}. So refactor driver to use function names easier to understand. This shouldn't affect the functionality though. Suggested-by: -
Sumit Garg authored
Add support for PCIe clocks required to enable PCIe support on iMX8MP SoC. Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by:
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- Mar 22, 2024
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Add APIs to set a firmware_name to a rproc and boot the rproc with the same firmware. Clients can call rproc_set_firmware() API to set firmware_name for a rproc whereas rproc_boot() will load the firmware set by rproc_set_firmware() to a buffer by calling request_firmware_into_buf(). rproc_boot() will then load the firmware file to the remote processor and start the remote processor. Signed-off-by:
MD Danish Anwar <danishanwar@ti.com> Acked-by:
Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by:
Roger Quadros <rogerq@kernel.org>
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The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain, and there are no C66x DSP subsystems on these SoCs. The C71x DSP subsystem is a slighly updated version of the C71x DSP subsystem on J721e. The C71x DSPs are 64 bit machine with fixed and floating point DSP operations. Extend support to the C71x DSPs with J721S2 compatible strings. Signed-off-by:
Hari Nagalla <hnagalla@ti.com> Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by:
Apurva Nandan <a-nandan@ti.com>
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The K3 J721S2 SoCs have three dual-core R5F subsystems, one in MCU voltage domain and the other two in MAIN voltage domain. These R5F clusters are similar to the R5F clusters in J7200 SoCs. Compatible Info is updated to support J721S2 SoCs. Signed-off-by:
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Since commit cc7df0b9 ("serial: lpuart: Enable IPG clock") the apalis-imx8qm board no longer boots. The reason is that the imx8qm clock driver does not handle the LPUART IPG clocks inside get_rate(), set_rate() and enable() functions. Fix the boot regression by adding the LPUART IPG entries. Fixes: cc7df0b9 ("serial: lpuart: Enable IPG clock") Reported-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com>
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Since commit cc7df0b9 ("serial: lpuart: Enable IPG clock") the colibri-imx8qxp board no longer boots. The reason is that the imx8qxp clock driver does not handle the LPUART IPG clocks inside get_rate(), set_rate() and enable() functions. Fix the boot regression by adding the LPUART IPG entries. Fixes: cc7df0b9 ("serial: lpuart: Enable IPG clock") Reported-by:
Sean Anderson <seanga2@gmail.com>
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- Mar 21, 2024
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efi_console / UEFI applications (grub2, sd-boot, ...) pass UTF-8 character sequences to vidconsole which results in wrong glyphs for code points outside of ASCII. The truetype console expects Unicode code points and bitmap font based consoles expect code page 437 code points. To support both convert UTF-8 to UTF-32 and pass Unicode code points in vidconsole_ops.putc_xy(). These can be used directly in console_truetype and after conversion to code page 437 in console_{normal,rotate}. This fixes rendering of international, symbol and box drawing characters used by UEFI applications. Signed-off-by:Janne Grunau <j@jannau.net>
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- Mar 20, 2024
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Signed-off-by:Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
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- Mar 18, 2024
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This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by:
Jit Loon Lim <jit.loon.lim@intel.com> Reviewed-by:
Tien Fong Chee <tien.fong.chee@intel.com>
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Add socfpga_dtreg driver enablement for Intel SoCFPGA. Signed-off-by:
Wan Yee Lau <wan.yee.lau@intel.com> Reviewed-by:
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- Mar 17, 2024
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Benjamin Hahn authored
The polling rate is already specified in some devicetrees, like imx8mp.dtsi for example, but was not selected so far. For the trippoints, the cpu-thermal node is used. Also get the polling rate from this node. Use the default of 5000ms if the polling rate should not be specified in the devicetree. NOTE: The polling rate from the devicetree will be used after this patch. In imx8*.dtsi devicetrees the polling delay is set to 2000ms for example. Signed-off-by:
Benjamin Hahn <B.Hahn@phytec.de> Reviewed-by:
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- Mar 14, 2024
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The BUTTON_ADC symbol guards the compilation of button-adc driver whose name very well makes it explicit that it requires ADC support to be enabled. Fix build issue of button-adc driver when ADC support isn't enabled by making sure it cannot be built without ADC support. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com> Signed-off-by:
Quentin Schulz <quentin.schulz@theobroma-systems.com>
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The ADC controller drivers are obviously all depending on ADC symbol being selected. While they don't seem to fail to build without, they won't be useful without that symbol selected, so let's make sure the options aren't shown in menuconfig when ADC isn't selected. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it difficult to know at first glance in menuconfig what's for what, let's fix this by adding "in SPL" at the end of the prompt for the SPL symbol. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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This adds support for the SARADCv2 found on RK3588. There is no stop callback as it is currently configured in single conversion mode, where the ADC is powered down after a single conversion has been made. Due to what seems to be a silicon bug, a controller reset needs to be issued before starting a channel conversion otherwise Rockchip says that channel 1 will error whatever that means. This is aligned with upstream and downstream Linux kernel as well as downstream U-Boot. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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SARADC v2 doesn't have a stop mechanism once in single mode. In series conversion, the logic is different anyway. Therefore, let's abstract this function so that it can be provided from the udevice.data pointer. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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SARADC v1 and v2 have a different way of starting a channel, therefore let's abstract this function so that it can be provided from the udevice.data pointer. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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SARADC v1 and v2 have a different way of reading data, therefore let's abstract this function so that it can be provided from the udevice.data pointer. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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The registers are entirely different between SARADC v1 and SARADC v2, so let's prepare to add another struct for accessing v2 registers by adding a union. Cc: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by:
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