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    • Tom Rini's avatar
      test/py: Make the number of SPL banners seen a variable · 645f75f6
      Tom Rini authored
      
      Currently we have the option to tell the console code that we should
      ignore the SPL banner. We also have an option to say that we can see it
      a second time, and ignore it. However, some platforms such as TI AM64x
      will have us see the SPL banner three times. Rather than add an
      "spl3_skipped" option, rework the code. By default we expect to see the
      banner once, but boards can specify seeing it as many times as they
      expect to.
      
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      645f75f6
    • Boon Khai Ng's avatar
      net: Add drivers for Sysnopsys Ethernet 10G device · 48022fb4
      Boon Khai Ng authored and Tom Rini's avatar Tom Rini committed
      
      This driver support the Synopsys Designware Ethernet 10G
      IP block refer from the driver dwc_eth_qos.
      
      The driver MAC register mapping is different between
      Synopsys QoS IP and Synopsys 10G IP, and thus new file
      is created meant for Sysnopsys 10G IP.
      
      The dwc_eth_xgmac_socfpga.c is specific to a device family,
      the driver support the specific configuration used in
      Intel SoC FPGA Agilex5.
      
      This driver is extensible for other device family to use.
      
      Signed-off-by: default avatarBoon Khai Ng <boon.khai.ng@intel.com>
      48022fb4
    • Tom Rini's avatar
      Merge patch series "arm: Add Analog Devices SC5xx Machine Type" · 1afa75c0
      Tom Rini authored
      Greg Malysa <greg.malysa@timesys.com> says:
      
      This series adds support for the ADI SC5xx machine type and includes two
      core drivers that are required for being able to boot any board--a UART
      driver, the gptimer driver which is used as a clock reference (CNTVCNT
      is not supported on the armv7 sc5xx SoCs) and the clock tree driver. Our
      corresponding Linux support relies on u-boot configuring the clocks
      correctly before booting, so it is not possible to boot any board
      without the CGU/CDU configuration happening here. There are also no
      board files, device trees, or defconfigs included here, but some common
      definitions that will be used to build board files currently are. The
      sc5xx SoCs themselves include many armv7 families (sc57x, sc58x, and
      sc594) all using an ARM Cortex-A5, and one armv8 family (sc598) indended
      to be a drop-in replacement for the SC594 in terms of peripherals, with
      a Cortex-A55 instead.
      
      Some of the configuration code in dmcinit and clkinit is quite scary and
      causes a lot of checkpatch violations. It is modified from code
      initially provided by ADI, but it has not been fully rewritten. There's
      a question of how important it is to clean up this code--it has some
      quality violations, but it has been in use (including in production) for
      over two years and is known to work for performing the low level SoC
      initialization, while a rewrite might introduce timing or sequence bugs
      that could take a significant amount of time to detect in the future.
      1afa75c0
    • Greg Malysa's avatar
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