- Feb 08, 2022
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Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com>
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Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by:
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PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by:
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Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by:
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Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by:
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No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by:
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Add support to get SSC type from DT. Signed-off-by:
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Add binding to specify Spread Spectrum Clocking mode used Signed-off-by:
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Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by:
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The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the function device_probe, the corresponding clocks are probed before calling the device's probe. The PLL_CMNLC mux clock can only be created after the device's probe. Therefore, move assigned-clocks and assigned-clock-parents to the link nodes in U-Boot device tree file. Signed-off-by: -
Add support for probing, initializing and powering, SerDes0 instance. Signed-off-by: -
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: -
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's possible to select one of these two inputs from device tree. Signed-off-by: -
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes instance. Signed-off-by: -
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by:
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No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by:
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No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by:
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Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by:
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Commit 39b82338 ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Signed-off-by:
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Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by:
Sanket Parmar <sparmar@cadence.com> Signed-off-by:
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Add support for ipu early boot. Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Amjad Ouled-Ameur <aouledameur@baylibre.com>
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Add support for ipu early boot. Signed-off-by:
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Add ipu and the associated nodes. Signed-off-by:
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Add all the ipu early boot related nodes Signed-off-by:
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The driver enables IPU support. Basically enables the clocks, timers, watchdog timers and bare minimal MMU and supports loading the firmware from mmc. Signed-off-by:
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Add remoteproc resource handling helpers. These functions are primarily to parse the resource table and to handle different types of resources. Carveout, devmem, trace & vring resources are handled. Signed-off-by:
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Add find_next_zero_area to fetch the next zero area in the map. Signed-off-by:
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Enable fs_loader compilation at SPL Level. Signed-off-by:
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First check the presence of the ipu firmware in the boot partition. If present enable the ipu and the related clocks & then move on to load the firmware and eventually start remoteproc IPU1/IPU2. do_enable_clocks by default puts the clock domains into auto which does not work well with reset. Hence adding do_enable_ipu_clocks function. Signed-off-by:
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Add a reset driver to bring IPs out of reset. Signed-off-by:
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Expand SPL_MULTI_DTB_FIT to accommodate new SPL IPU nodes. Signed-off-by: -
There is a 4 bit VARIANT number inside the JTAGID register that TI increments any time a new variant for a chip is produced. Each family of TI's SoCs uses a different versioning scheme based off that VARIANT number. CC: Dave Gerlach <d-gerlach@ti.com> Signed-off-by:
Bryan Brattlof <bb@ti.com> -
Enable A72 specific configs for J721S2 Signed-off-by:
David Huang <d-huang@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
Hari Nagalla <hnagalla@ti.com>
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Enable R5 SPL specific configs for J721S2. Signed-off-by:
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J721S2 can support two instances for DDR. Therefore, add the device support for the same and use 4266MT/s as DDR frequency. Signed-off-by: -
Add initial support for device tree that runs on R5. Signed-off-by: -
The EVM architecture for J721S2 is similar to that of J721E and J7200. It is as follows, +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the common processor baord. Therefore, add support for peripherals brought out in the common processor board. Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439 Signed-off-by: -
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Therefore, add support for the components present on the SoM. Signed-off-by: -
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by:
Nishanth Menon <nm@ti.com>
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