- Feb 05, 2022
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When using a board variant that selects the lvds specific dtb the *.u-boot.dtsi file will not be included. To have a lvds dtb specific u-boot.dtsi file move this part to a common board u-boot.dtsi file and include this in the board base u-boot.dtsi and create an additional one for the lvds variant. Signed-off-by:
Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by:
Frieder Schrempf <frieder.schrempf@kontron.de>
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CONFIG_SPL_MMC and CONFIG_SPL_SERIAL Signed-off-by:
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Without this patch the bcb struct could be located at an odd address which resulted in data not being copied to the buffer. Here was the repro steps (from Mattijs): => mmc dev 1 => bcb load 1 misc => bcb dump command 00000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 => part start mmc 1 misc misc_start => mmc read ${loadaddr} ${misc_start} 4 => bcb load 1 misc => bcb dump command 00000000: 62 6f 6f 74 6f 6e 63 65 2d 62 6f 6f 74 6c 6f 61 00000010: 64 65 72 00 00 00 00 00 00 00 00 00 00 00 00 00 This behavior was observed on an Amlogic A311D (ARM64) platform with a recent GCC toolchain (11.2.0) but is most likely affecting other platforms. To avoid issues the structure is aligned on DMA minimum alignment value as it is passed directly to the read function. Signed-off-by:Gary Bisson <gary.bisson@boundarydevices.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on khadas vim3
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We changed to single flash.bin now. So dfu_alt_info should be modified to reflect this change. Signed-off-by:
Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Reviewed-by:
Fabio Estevam <festevam@gmail.com>
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Add support of secondary boot address for imx8mn. The secondary boot address is hardcoded in the fuse. The value is calculated from there according to the following description: The fuse IMG_CNTN_SET1_OFFSET (0x490[22:19]) is defined as follows: - Secondary boot is disabled if fuse value is bigger than 10, n = fuse value bigger than 10. - n == 0: Offset = 4MB - n == 2: Offset = 1MB - Others & n <= 10 : Offset = 1MB*2^n - For FlexSPI boot, the valid values are: 0, 1, 2, 3, 4, 5, 6, and 7. Signed-off-by:Michael Trimarchi <michael@amarulasolutions.com>
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Similar to what has been done before with c5437e5b for u-boot proper, we enable the SMP bit for SPL as well. This is necessary when SDP booting straight into Linux, i.e. falcon boot. When SDP boot mode is active, the ROM code does not set this bit which makes the caches not work once activated in Linux. On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into an initramfs shell from ~6.1s down to ~1.2s. Signed-off-by:
Sven Schwermer <sven@svenschwermer.de> Reviewed-by:
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Skip running arch/arm/mach-imx flash.bin generation in case BINMAN is enabled, otherwise the target in arch/arm/mach-imx/Makefile regenerates the flash.bin again and produces corrupted result. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@oss.nxp.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12"). There is no functional change to the resulting DTs. The imx6qdl-dhcom-pdk2.dtsi had to be adjusted with additional headers, gpio.h, pwm.h, input.h, else the DT cannot be compiled, the same change is likely necessary in Linux. Signed-off-by: -
Add labels to remaining anatop regulators, so their supplies can be assigned in board DTs. This is similar to Linux kernel commit 93385546ba369 ("ARM: dts: imx6qdl-sabresd: Assign corresponding power supply for LDOs") except it does not contain the unrelated sabresd changes. Signed-off-by: -
This change enables the support for USB with DM on the XEA (imx28) board. Signed-off-by:Lukasz Majewski <lukma@denx.de>
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The new configs/imx28_xea_sb_defconfig is introduced to facilitate building the single binary u-boot.sb fox XEA board. The biggest distinction from "normal" XEA imx28_xea_sb_defconfig is support for USB mass storage devices (pen drives). To achieve that, the CONFIG_DM_USB is enabled and supported. Signed-off-by: -
Now the dts information corresponds to the one available in the kernel. With this patch applied the 'mtd list' shows proper names and offsets for MTD partitions. Signed-off-by: -
This change provides the possibility to build XEA (imx287 based) board U-Boot as a single binary (without support for CONFIG_SPL_FRAMEWORK). The generated u-boot.sb can be used in the factory environment to for example perform initial setup or HW testing. It can be used with 'uuu' utility (SDPS: boot -f /srv/tftp/xea/u-boot.sb) In the configs/imx28_xea_defconfig one needs to disable following configs: # CONFIG_SPL_BLK is not set # CONFIG_SPL_FRAMEWORK is not set The board_init_ll() is used in arch/arm/cpu/arm926ejs/mxs/start.S, which is utilized when CONFIG_SPL_FRAMEWORK is disabled. However, when it is enabled - the arch/arm/cpu/arm926ejs/start.S is used, which requires the lowlevel_init() function. Signed-off-by: -
With the current configuration provided in mxsimage{-spl}.mx28.cfg the size of SPL binary has been constrained to 32 KiB, due to "LOAD IVT" command with 0x8000 offset. The problem was that, the imx28 ROM takes the u-boot.sb and then extracts from it the IVT header and places it on the 0x8000 OCRAM offset overwriting any valid (i.e. loaded from eMMC or SPI-NOR) SPL code. This bug was unnoticed as the overwrite size was just 32 bytes, so the probability that some important code is altered was low. However, in the XEA board (where the SPL size is ~39KiB), the overwritten data was `(struct dm_spi_ops *) 0x800c <mxs_spi_ops>`, which is used during the boot process. As a result the SPL execution code hanged with "undefined instruction" abort as callbacks (with wrong addresses) from it were called. The fix is to change the OCRAM's offset where IVT is loaded to 0xE000, so the SPL can grow up to ~57KiB (the maximal size of OCRAM memory available is 0xE3FC). Signed-off-by: -
According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may have the ESAI_TX0 functionality, not ESAI_T0. Also, NXP's i.MX Config Tools 10.0 generates dtsi with the MX6ULL_PAD_CSI_DATA07__ESAI_TX0 naming, so fix it accordingly. There are no devicetree users in mainline that use the old name, so just remove the old entry. Fixes: f8ca22b8 ("arm: dts: imx6ull: add pinctrl defines") Reported-by:
George Makarov <georgemakarov1@gmail.com> Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Use imx6_src_get_boot_mode() instead of manually reading SBMR1. The existing function has proper handling for software overrides of the bootdevice which can happen, for example, when booting from an alternate source using `bmode`. Signed-off-by:
Harald Seiler <hws@denx.de>
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The PDK2 board is capable of running both 100M and 1G ethernet. However, the i.MX6 has only one ethernet MAC, so it is possible to configure either 100M or 1G Ethernet. In case of 100M option, the PHY is on the SoM and the signals are routed to a RJ45 port. For 1G the PHY is on the PDK2 board with another RJ45 port. 100M and 1G ethernet use different signal pins from the i.MX6, but share the MDIO bus. This SoM board combination is used to demonstrate how to enable 1G ethernet configuration. Signed-off-by:
Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by:
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If `sb_load_cmdfile()` fails to open the configuration file it will jump to error handling where the code will try to `fclose()` the FILE pointer which is NULL causing `mkimage` to segfault. This patch removes the label for error handling and instead returns immediately which skips the `fclose()` and prevents the segfault. The errno is also described in the error message to guide users. Signed-off-by:
Mattias Hansson <hansson.mattias@gmail.com> Reviewed-by:
Wolfgang Denk <wd@denx.de>
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Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: - 1GiB DDR4 RAM - 16 GiB eMMC - SD card - Gigabit ethernet - USBOTG1 peripheral - fastboot Signed-off-by:
Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
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The FXL6408 GPIO expander manages critical devices, including on-module USB hub. Configure the expander to switch the USB hub into bypass mode, allowing to use on-carrier-board USB hub. Signed-off-by:
Oleksandr Suvorov <cryosay@gmail.com> Signed-off-by:
Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
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Initial support for Fairchild's 8 bit I2C gpio expander FXL6408. The CONFIG_FXL6408_GPIO define enables support for such devices. Based on: https://patchwork.kernel.org/patch/9148419/ Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by:
Heiko Schocher <hs@denx.de> Signed-off-by:
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Previously these two options are called CONFIG_SPL_MMC_SUPPORT and CONFIG_SPL_SERIAL_SUPPORT. During the transition they are removed by accident. Thus adding them back. Signed-off-by:
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The value of cnt is overwritten without being used. Signed-off-by:
Haolin Li <li.haolin@qq.com> Reviewed-by:
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Extension boards can be added to Compulab's iot-gate-imx8mm. We implement extension board manager for detecting the extension boards. Signed-off-by:
Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by:
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add the following overlays: - IED extension board - CAN/TPM/ADC extension board on IED board. Signed-off-by:
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After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by:
Ye Li <ye.li@nxp.com> Signed-off-by:
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On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by:
Jacky Bai <ping.bai@nxp.com> Signed-off-by:
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Obatin the SoC current temperature in print_cpuinfo(). Reviewed-by:
Alice Guo <alice.guo@nxp.com> Signed-off-by:
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The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by:
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This patch implements enable_adc1_clk() to enable or disable the ADC1 clock on i.MX8ULP. Reviewed-by:
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Get the MAC address from fuse bank5 word 3 and 4. It has MSB first at lowest address, so have a reverse order with other iMX used in mac.c Reviewed-by:
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When LPAV is allocated to RTD, the LPAV won't be reset. So we have to reset DCNano and MIPI DSI in u-boot before enabling the drivers Reviewed-by:
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The LPAV is not allocated to APD when dual boot, so LPAV won't reset when APD is reset. We have to explicitly reset the DDR, otherwise its initialization will fail. Reviewed-by:
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8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0 LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision. A0.2 will fix the issue in ROM. But A0.1 we have to workaround it in SPL by setting LPOSCCTRL BIASCURRENT again. Reviewed-by:
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Remove the freescale vendor name from CPU revision print to align with other i.MX platforms Reviewed-by:
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The setting does not have effect because we should set it after power on the PS16 for NIC AV. So move it after upower_init which has powered on all PS Reviewed-by:
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To avoid DCNANO underrun issue on high loading test, set its read Qos on NIC_LPAV to highest Reviewed-by:
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The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and backlight. However the LPI2C0 and TPM0 are M33 resources, in this patch we simply access them, but this is a temporary solution. We will modify it when M33 FW changes to set MIPI DSI panel as default path and enable backlight after reset. Signed-off-by:
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For singel boot, set flexspi0 mem to be accessed by A35 Signed-off-by:
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Add the DSI clock enable and disable with PCC reset used. Add the LCD pixel clock calculation and configuration for DCNano Signed-off-by:
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