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  1. Jan 14, 2022
    • This contributor prefers not to receive mails's avatar
      board: gdsys: a38x: Enable PCIe link 2 in spl_board_init() · 2ac06f3e
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      A385 controlcenterdc board does not use PCI DM properly and touches some
      PCIe devices directly in its board code.
      
      This controlcenterdc spl_board_init() function expects that PCIe link is
      already initialized. Link itself is initialized in a38x serdes code but
      this will change in future and link initialization will be postponed from
      U-Boot SPL to proper U-Boot.
      
      So explicitly enable PCIe link 2 in spl_board_init() function via
      SoC Control Register 1 to not break this code by future changes. This board
      has PCIe link 2 just x1, so no additional initialization (except enabling
      PCIe port) is needed.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      2ac06f3e
    • This contributor prefers not to receive mails's avatar
      arm: mvebu: Convert board_pex_config() to CONFIG_SPL_BOARD_INIT · 8f9e0f4d
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      The only user of board_pex_config() weak function is A385 controlcenterdc
      board. It looks like that code in its board_pex_config() function needs to
      be executed after PCIe link is up. Therefore put this code into
      spl_board_init() function which is called after a38x serdes initialization,
      and therefore it is after the serdes hws_pex_config() function finishes
      (which is the state before this change).
      
      With this change completely remove board_pex_config() function as it is not
      used anymore.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      8f9e0f4d
  2. Jan 13, 2022
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