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  1. Jan 14, 2022
    • This contributor prefers not to receive mails's avatar
      pci: pci_mvebu: Split initialization of PCIe ports into 3 phases · afef9f42
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      In first phase just parse DT properties and fill struct mvebu_pcie. In
      second phase setup all PCIe links (without enabling them). And in the last
      third phase enable all PCIe links and create UCLASS_PCI device for each
      one.
      
      Because parsing of DT is done before UCLASS_PCI is created, we cannot use
      DM for this action anymore. So remove .of_to_plat callback and replace it
      by ad-hoc function for parsing DT properties and filling struct mvebu_pcie.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      afef9f42
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      pci: pci_mvebu: Remove dependency on SOC_REGS_PHY_BASE macro · 137db2af
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      SoC specific macro SOC_REGS_PHY_BASE is used for two things:
      
      * calculation of base PCIe port address
      * filling PCIe register with address of internal registers
      
      For calculating base PCIe port address use function
      ofnode_translate_address() which translates DT "assigned-addresses" to
      final PCIe port address.
      
      And for calculating address of internal registers use untranslated and
      translated DT "assigned-addresses".
      
      Basically this change reads SOC_REGS_PHY_BASE address indirectly from DT.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      137db2af
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      pci: pci_mvebu: Inline mvebu_pcie_port_parse_dt() function · 6f4988f9
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      Function mvebu_pcie_port_parse_dt() is called only from
      mvebu_pcie_of_to_plat() function. Both these function parse DT properties
      required to setup mvebu pcie. So inline mvebu_pcie_port_parse_dt() function
      into mvebu_pcie_of_to_plat() to have all code related to parsing DT
      properties at one place.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      6f4988f9
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      pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping · 537b0142
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      Do not call pci_set_region() for resources which were not properly mapped.
      This prevents U-Boot to access unmapped memory space.
      
      Update MBUS_PCI_MEM_SIZE and MBUS_PCI_IO_SIZE macros to cover all PCIe MEM
      and IO ranges. Previously these macros covered only address ranges for the
      first PCIe port. Between MBUS_PCI_IO_BASE and MBUS_PCI_MEM_BASE there is
      space for six 128 MB long address ranges. So set MBUS_PCI_MEM_SIZE to value
      of 6*128 MB. Similarly set MBUS_PCI_IO_SIZE to 6*64 KB.
      
      Function resource_size() returns zero when start address is 0 and end
      address is -1. So set invalid resources to these values to indicate that
      resource has no mapping.
      
      Split global PCIe MEM and IO resources (defined by MBUS_PCI_*_* macros)
      into PCIe ports in mvebu_pcie_bind() function which allocates per-port
      based struct mvebu_pcie, instead of using global state variables
      mvebu_pcie_membase and mvebu_pcie_iobase. This makes pci_mvebu.c driver
      independent of global static variables (which store the state of
      allocation) and allows to bind and unbind the driver more times.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Signed-off-by: default avatarMarek Behún <marek.behun@nic.cz>
      537b0142
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      board: gdsys: a38x: Enable PCIe link 2 in spl_board_init() · 2ac06f3e
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      A385 controlcenterdc board does not use PCI DM properly and touches some
      PCIe devices directly in its board code.
      
      This controlcenterdc spl_board_init() function expects that PCIe link is
      already initialized. Link itself is initialized in a38x serdes code but
      this will change in future and link initialization will be postponed from
      U-Boot SPL to proper U-Boot.
      
      So explicitly enable PCIe link 2 in spl_board_init() function via
      SoC Control Register 1 to not break this code by future changes. This board
      has PCIe link 2 just x1, so no additional initialization (except enabling
      PCIe port) is needed.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      2ac06f3e
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      arm: mvebu: Convert board_pex_config() to CONFIG_SPL_BOARD_INIT · 8f9e0f4d
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      The only user of board_pex_config() weak function is A385 controlcenterdc
      board. It looks like that code in its board_pex_config() function needs to
      be executed after PCIe link is up. Therefore put this code into
      spl_board_init() function which is called after a38x serdes initialization,
      and therefore it is after the serdes hws_pex_config() function finishes
      (which is the state before this change).
      
      With this change completely remove board_pex_config() function as it is not
      used anymore.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      8f9e0f4d
  2. Jan 13, 2022
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