- Dec 26, 2019
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USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar to erratum A-009007, but this one is for LX2160A, and the register value is different. Signed-off-by:
Ran Wang <ran.wang_1@nxp.com> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com>
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Mark board_fit_config_name_match() as weak so a board can overwrite the empty function. Signed-off-by:
Michael Walle <michael@walle.cc> Reviewed-by:
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Maximum size of secure boot header to be read from MMC is 12KB which spans across 0x20 blocks. Hence increase the mmc read size for secure boot headers from MMC to 0x20 blocks. Signed-off-by:
Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by:
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Add support for DPSPARSER object (create/destroy, open/close, apply spb) which is required to configure Soft Parser by using MC. Also add uboot command to apply Soft Parser Blob with command: fsl_mc apply spb <spb_load_addr> Signed-off-by:
Florinel Iordache <florinel.iordache@nxp.com> Signed-off-by:
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- Dec 24, 2019
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https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini authored
- Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards
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- Dec 23, 2019
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This is the first step to use DM support for the KM powerpc boards. Signed-off-by:
Holger Brunck <holger.brunck@ch.abb.com> Reviewed-by:
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Some of t1042 boards fails DDR init with an Automatic calibration error every now and then. Investigations revealed that true Warm boots never failed. Warm boots has some extra steps performed, one being to start DDRC in Self Refresh and then clearing SR right after. Applying this SR method unconditionally made all our boards stable again, regardless of Cold/Warm boot. Signed-off-by:
Joakim Tjernlund <joakim.tjernlund@infinera.com> Signed-off-by:
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CONFIG_CONS_INDEX is nowhere used for this board, we can drop it. Signed-off-by:
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We can use the existing CONFIG_SYS_CONFIG_NAME define for that and remove the option. Also fix the boot string for all km83xx boards. Signed-off-by:
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Remove this from the board header files and move it to Kconfig. Also use the correct default address for kmtegr1. Signed-off-by:
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On kmtegr1 we have to specify the second localbus clock signal also instead of using the default for our ppc 8309 boards. Signed-off-by:
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- Dec 18, 2019
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https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini authored
- Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral
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- Dec 17, 2019
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https://gitlab.denx.de/u-boot/custodians/u-boot-i2cTom Rini authored
i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it.
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Add ability to query size of eeprom device and partitions Signed-off-by:
Robert Beckett <bob.beckett@collabora.com> Reviewed-by:
Heiko Schocher <hs@denx.de>
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Add ability to partition eeprom via devicetree bindings Signed-off-by:
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Add support for setting the chip address offset mask to EEPROM sumulator and add tests to test it. Signed-off-by:
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Improve i2c EEPROM simulator testing by providing access functions to check the previous chip addr and offset. Given that we can now directly test the offsets, also simplified the offset mapping and allow for wrapping acceses. Signed-off-by:
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Some devices (2 wire eeproms for example) use some bits from the chip address to represent the high bits of the offset instead of or as well as using multiple bytes for the offset, effectively stealing chip addresses on the bus. Add a chip offset mask that can be set for any i2c chip which gets filled with the offset overflow during offset setup. Signed-off-by:
Ian Ray <ian.ray@ge.com> Reviewed-by:
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- Dec 15, 2019
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Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> -
The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
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