- Apr 28, 2021
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When zImage support was added to SPL, the messages were hidden to reduce code size. However, the wrong config symbol was used. Since this file is only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden. Use the correct symbol so the messages are printed in U-Boot proper. Also use IS_ENABLED to drop the #ifdef. Fixes: 431889d6 ("spl: zImage support in Falcon mode") Signed-off-by:
Samuel Holland <samuel@sholland.org>
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When flush_cache() is called during boot on our ~7M kernel image, the hundreds of thousands of WATCHDOG_RESET calls end up adding significantly to boottime. Flushing a single cache line doesn't take many microseconds, so doing these calls for every cache line is complete overkill. The generic watchdog_reset() provided by wdt-uclass.c actually contains some rate-limiting logic that should in theory mitigate this, but alas, that rate-limiting must be disabled on powerpc because of its get_timer() implementation - get_timer() works just fine until interrupts are disabled, but it just so happens that the "big" flush_cache() call happens in the part of bootm where interrupts are indeed disabled. [1] [2] [3] I have checked with objdump that the generated code doesn't change when this option is left at its default value of 0: gcc is smart enough to see that the ">=" comparison is tautologically true, hence all assignments to "flushed" are eliminated as dead stores. On our board, setting the option to something like 65536 ends up reducing total boottime by about 0.8 seconds. [1] https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villemoes@prevas.dk/ [2] https://lists.denx.de/pipermail/u-boot/2021-April/446906.html [3] https://lists.denx.de/pipermail/u-boot/2021-April/447280.html Reviewed-by:
Stefan Roese <sr@denx.de> Signed-off-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk>
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CONFIG_5xx hasn't existed since commit 50258977 (powerpc, 5xx: remove support for 5xx). Remove this last mention of it. Reviewed-by:
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Having WATCHDOG_RESET() called automatically from the timer interrupt runs counter to the idea of a watchdog device - if the board runs into an infinite loops with interrupts still enabled, the watchdog will never fire. When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more complicated than just poking a few SOC-specific registers - it involves accessing all kinds of global data, and if the interrupt happens at the wrong time (say, in the middle of an WATCHDOG_RESET() call from ordinary code), that can end up corrupting said global data. Allow the board to opt out of calling WATCHDOG_RESET() from the timer interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that setting is currently nonsensical (it would be compile-time divide-by-zero), it cannot affect any existing boards. Add documentation for both the existing and extended meaning of CONFIG_SYS_WATCHDOG_FREQ. Signed-off-by: -
The code, which is likely copied from arch/powerpc/lib/interrupts.c, lacks a fallback definition of CONFIG_SYS_WATCHDOG_FREQ and refers to a non-existing timestamp variable - obviously priv->timestamp is meant. Signed-off-by: -
Some boards don't work with the rate-limiting done in the generic watchdog_reset() provided by wdt-uclass. For example, on powerpc, get_timer() ceases working during bootm since interrupts are disabled before the kernel image gets decompressed, and when the decompression takes longer than the watchdog device allows (or enough of the budget that the kernel doesn't get far enough to assume responsibility for petting the watchdog), the result is a non-booting board. As a somewhat hacky workaround (because DT is supposed to describe hardware), allow specifying hw_margin_ms=0 in device tree to effectively disable the ratelimiting and actually ping the watchdog every time watchdog_reset() is called. For that to work, the "has enough time passed" check just needs to be tweaked a little to allow the now==next_reset case as well. Suggested-by:
Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by:
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Signed-off-by:Tom Rini <trini@konsulko.com>
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Enable support for PCIe NVMe devices. Signed-off-by:Marek Vasut <marek.vasut+renesas@gmail.com>
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Enable CONFIG_SYS_FLASH_PROTECTION on Salvator-X(S), ULCB, Ebisu, which means the Spansion HF PPB protection bits can be operated using the 'protect' U-Boot command. Signed-off-by: -
Synchronize Gen2 MSTP teardown tables with datasheet Rev.2.00 Feb 01, 2016. This corrects the following bits: - added H2 MSTP3[10] SCIF2 - added H2/M2/E2 MSTP7[29] TCON - removed E2 MSTP5[22] Thermal Sensor - removed E2 MSTP10[31,24:22] SRC0, SRC7:9 Signed-off-by: -
The clock driver used a heavy-handed approach where it turned off all available clocks, while also possibly setting bits which are not documented in the R-Car datasheet. Update the tables so that only the bits which are documented are set or cleared when tearing down the clock driver. Note that the only clock left running before booting Linux are now MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x. Signed-off-by: -
Import updated devicetree files from the Linux v5.12 release. Besides some node and audio port renames this changes the PHY modes to either rgmii-id or rgmii-txid. From the board files the Pinephone sees a lot of updates. This also adds the long missing USB PHY property for controller 0, which allows the U-Boot PHY driver to eventually use port 0 in host mode (pending another U-Boot patch). Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Reviewed-by:
Jernej Skrabec <jernej.skrabec@siol.net>
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Update R40 .dts{,i} and dt-binding headers to current version from kernel. Files taken from Linux 5.12-rc1 release (commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8) Signed-off-by:Ivan Uvarov <i.uvarov@cognitivepilot.com> Reviewed-by:
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Commit eb5a2b67 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by:
Ramon Fried <rfried.dev@gmail.com>
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This patch adds support for the following I2C devices connected to I2C bus 0 on the Octeon EBB7304: - Dallas DS1337 RTC - TLV EEPROM Signed-off-by:
Aaron Williams <awilliams@marvell.com> Signed-off-by:
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We already have a clock driver for MIPS Octeon. This patch changes the Octeon DT nodes to supply the clock property via the clock driver instead of using an hard-coded value, which is not correct in all cases. Signed-off-by:
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Stefan Roese authored
This patch adds the basic support for the PCIe target board equipped with the Octeon III CN2350 SoC. Signed-off-by: -
Stefan Roese authored
Add the AHCI compatible SATA DT node to the Octeon CN73xx dtsi file. Signed-off-by: -
Stefan Roese authored
Otherwise the output will look like this on MIPS Octeon NIC23: Device 0: (0:0) Vendor: ATA Prod.: aSDnsi klUrt aII Rev: 4X11 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512) instead of this version: Device 0: (0:0) Vendor: TA Prod.: SanDisk Ultra II Rev: X411 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512) Signed-off-by: -
Stefan Roese authored
This patch adds a few missing virt_to_phys() to use the correct physical address for DMA operations in the common AHCI code. This is done to support the big-endian MIPS Octeon platform. Additionally the code a cleaned up a bit (remove some empty lines) and made a bit better readable. Signed-off-by: -
Stefan Roese authored
This patch enables the usage of the MVEBU AHCI/SATA driver. The only changes necessary to support MIPS Octeon via DT based probing are, to add the compatible DT property and the use of dev_remap_addr() so that the correct mapped address is used in the Octeon case (phys != virt). Please note that this driver supports the usage of the "scsi" command and not the "sata" command, since it does not provide an own "scan" function, which is needed for the "sata" cmd support. Signed-off-by: -
Stefan Roese authored
For easy AHCI/ SATA integration, this patch adds board_ahci_enable() for the MVEBU AHCI driver, which will be used by this platform. This platform specific "enable" function will setup the proper endian swapping in the AHCI controller so that it can be used by the common AHCI code. Additionally the endian swizzle entry for AHCI in octeon_should_swizzle_table[] is removed, as this enabled the original lowlevel code function, e.g. octeon_configure_qlm(), for the QLM setup to work correctly. Signed-off-by: -
Stefan Roese authored
This patch adds the necessary platform infrastructure code, so that the MIPS Octeon drivers "serial_octeon_pcie_console" & "serial_bootcmd" can be used. This is e.g. the bootmem initialization in a compatible way to the Marvell 2013 U-Boot, so that the exisiting PC remote tools like "oct-remote-console" & "oct-remote-load" can be used. This is be done in the newly introduced arch_misc_init(), which calls the necessary init functions when enabled. These patches are in preparation for the MIPS Octeon NIC23 board support, which is a desktop PCIe target board enabling these features. Signed-off-by: -
Stefan Roese authored
This patch adds the PCI bootcmd feature for MIPS Octeon, which will be used by the upcoming Octeon III NIC23 board support. It enables the use of the "oct-remote-load" and "oct-remote-bootcmd" on host PC's to communicate with the PCIe target and load images into the onboard memory and issue commands. Signed-off-by: -
Stefan Roese authored
This patch adds the PCI remote console feature for MIPS Octeon, which will be used by the upcoming Octeon III NIC23 board support. It enables the use of the "oct-remote-console" tool on host PC's to communicate with the PCIe target. Signed-off-by: -
Stefan Roese authored
As DEBUG is no Kconfig symbol, we can't use the IS_ENABLED() macros. This patch switches to the unfortunately necessary #ifdef usage again to make it work correctly. Signed-off-by: -
Stefan Roese authored
While porting from the Marvell source, I introduced a bug by misplacing the parenthesis. This patch fixes this issue. Signed-off-by: -
Stefan Roese authored
This makes is easier to use this macro from non-DDR related files. Signed-off-by: -
Stefan Roese authored
This patch changes the MIPS Octeon defconfig to enable some features for PCIe enablement. This includes CONFIG_BOARD_LATE_INIT to call the board specific serdes init code. With these features enabled, the serdes and PCIe driver including the Intel E1000 driver can be tested on the Octeon EBB7304. Signed-off-by: -
Stefan Roese authored
This patch adds the PCIe host controller driver for MIPS Octeon II/III. The driver mainly consist of the PCI config functions, as all of the complex serdes related port / lane setup, is done in the serdes / pcie code available in the "arch/mips/mach-octeon" directory. Signed-off-by: -
This patch adds the board specific QLM/DLM init code to the Octeon 3 EBB7304 board. The configuration of each port is read from the environment exactly as done in the 2013 U-Boot version to keep the board and it's configuration compatible. Signed-off-by:
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Stefan Roese authored
This patch adds the PCIe controller node to the MIPS Octeon 73xx dtsi file. Signed-off-by: -
Stefan Roese authored
Setting CONFIG_SYS_PCI_64BIT is needed for correct PCIe functionality on MIPS Octeon. Signed-off-by: -
Stefan Roese authored
This patch adds the newly added C files to the Makefile to enable compilation. This is done in a separate step, to not introduce build breakage while adding the single files with potentially missing externals. Signed-off-by: -
Import octeon_qlm.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by:
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Import octeon_fdt.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by:
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Import cvmx-qlm.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by:
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Import cvmx-pcie.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by:
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Import cvmx-helper.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by:
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Import cvmx-helper-util.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by:
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