- Sep 15, 2020
-
-
Add spi and spi nor flash nodes for am335x-icev2. Signed-off-by:Faiz Abbas <faiz_abbas@ti.com>
-
Signed-off-by:Matwey V. Kornilov <matwey.kornilov@gmail.com>
-
If devtype variable is setted via setenv, then the following devtype=X style is ignored. Currently, many u-boot commands use devtype variable in the latter manner: mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi Use devtype=mmc instead of setenv devtype mmc to avoid bugs with booting from another devtype. Signed-off-by: -
Enable the FS_LOADER and associated configs in the j7200_evm_r5_defconfig so that the R5 SPL can support the loading of firmware files from a boot media/file system. Signed-off-by:Suman Anna <s-anna@ti.com>
-
Add a generic fs_loader node to the K3 J7200 R5 common board dts file and use it as the chosen firmware-loader so that it can be used for loading various firmwares from a boot media/filesystem in R5 SPL on K3 J7200 EVM. Signed-off-by: -
The R5 SPL on J7200 SoCs will be limited to booting just the MCU R5FSS0 R5F core in LockStep-mode at present, so add the two required environment variables 'addr_mcur5f0_0load' and 'name_mcur5f0_0fw' that are needed by the R5 SPL early-boot logic. The firmware name used is also different from that on J721E SoCs. Signed-off-by: -
The A72 U-boot can support early booting of any of the Main or MCU R5F remote processors from U-boot prompt to achieve various system usecases before booting the Linux kernel. Update the default BOOTCOMMAND to provide an automatic and easier way to start various remote processors through added environment variables. Signed-off-by: -
The J7200 SoCs has two R5F sub-systems. Enable the TI K3 R5F remoteproc driver and the remoteproc command options to allow these R5F processors to be booted from A72 U-Boot. The Kconfigs are added using savedefconfig. Signed-off-by: -
The J7200 SoCs have different number of remote processors, but reuse the same environment settings as the J721E SoCs. The current env variable rproc_fw_binaries is geared towards J721E SoCs and is incorrect for J7200 SoCs. Please see the logic originally added in commit 0b4ab9c9 ("env: ti: j721e-evm: Add support to boot rprocs including R5Fs and DSPs"). Fix this by defining the DEFAULT_RPROCS macro appropriately using the corresponding TARGET_EVM Kconfig symbol. This macro is used by the 'rproc_fw_binaries' env variable in the common remoteproc env header file k3_rproc.h. The list of R5F cores to be started before loading and booting the Linux kernel are as follows, and mainly comprises of the Main R5FSS0 cores in this order: Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw The MCU R5FSS0 is in LockStep mode and is expected to be booted by R5 SPL, so it is not included in the list. The order of rprocs to boot cannot be really modified as only the Main R5FSS0 cores are involved and Core0 has to be booted first always before the corresponding Core1. Signed-off-by:
-
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster is present within the MCU domain (MCU_R5FSS0), and the other one is present within the MAIN domain (MAIN_R5FSS0). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory. Add the DT node for the MAIN domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: -
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster is present within the MCU domain (MCU_R5FSS0), and the other one is present within the MAIN domain (MAIN_R5FSS0). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: -
The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: -
The K3 J7200 SoC family has a revised R5F sub-system and contains a subset of the R5F clusters present on J721E SoCs. The integration of these clusters is very much similar to J721E SoCs otherwise. The revised IP has the following two new features: 1. TCMs are auto-initialized during module power-up, and the behavior is programmable through a MMR bit controlled by System Firmware. 2. The LockStep-mode allows the Core1 TCMs to be combined with the Core0 TCMs effectively doubling the amount of TCMs available. The LockStep-mode on previous SoCs could only use the Core0 TCMs. This combined TCMs appear contiguous at the respective Core0 TCM addresses. Add the support to these clusters in the K3 R5F remoteproc driver using J7200 specific compatibles and revised logic accounting for the above IP features/differences. Signed-off-by: -
The K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with 2 R5F cores each, one in each of the MCU and MAIN voltage domains. These clusters are a revised version compared to those present on J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible info relevant to these R5F clusters/subsystems on K3 J7200 SoCs. Signed-off-by: -
The commit 316c9271 ("include: configs: j721e_evm: Add env variables for mcu_r5fss0_core0 & main_r5fss0_core0") added four different new env variables 'addr_mainr5f0_0load', 'name_mainr5f0_0fw', 'addr_mcur5f0_0load' and 'name_mcur5f0_0fw' to the generic environment, but these are only needed and used in R5 SPL for early-booting the MCU R5FSS0 and Main R5FSS0 Core0 on J721E SoCs. These are not really needed for A72 U-Boot, so limit the scope of these variables only to R5 SPL. While at this, also fix the loadaddr variable values to include the hex prefix like with other such env variables. Cc: Keerthy <j-keerthy@ti.com> Signed-off-by:
-
The default rproc list currently used by A72 U-Boot to boot various remote processors include the Main R5FSS0 (Split-mode) Core1, Main R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster is configured for Split mode by default in the dts now, so add the Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This core is now booted after the Main R5FSS1 Core0 and before the DSPs. The order of the rprocs to boot can always be changed at runtime if desired by overwriting the 'rproc_fw_binaries' environment variable at U-boot prompt. Note that the R5FSS Core1 cannot be booted before its associated Core0. Signed-off-by: -
Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the default so that two different applications can be run on each of the R5F cores in performance mode. LockStep-mode would be available only on SoCs efused with the appropriate bit, and Split-mode is the mode that is available on all J721E SoCs. Signed-off-by: -
Add memory mapped address location of U-Boot images in HyperFlash boot mode. Signed-off-by:Vignesh Raghavendra <vigneshr@ti.com>
-
Enable configs required to support HyperFlash boot and detection of onboard mux switch for HyperFlash selection Signed-off-by: -
Enable HyperBus and HyperFlash to support HyperFlash boot. Signed-off-by: -
On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of them can be used at any time. J7200 EVM has both HyperFlash and OSPI flash on board. There is a user switch (SW3.1) that can be toggled to select OSPI flash vs HyperFlash. Read the state of this switch via wkup_gpio0_6 line and fixup the DT nodes to select OSPI vs HyperFlash Signed-off-by: -
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode to NOR boot to enable SPL to load next stage using NOR boot flow. Signed-off-by:
-
- Sep 07, 2020
-
-
Tom Rini authored
Signed-off-by:Tom Rini <trini@konsulko.com>
-
Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by: -
https://gitlab.denx.de/u-boot/custodians/u-boot-efiTom Rini authored
Pull request for UEFI sub-system for efi-2020-10-rc4 Bug fixes are provided in the following areas: * convert file system debug and print messages go log messages * convert UEFI booting messages to log messages * UEFI related code clean up and simplification
-
- Sep 06, 2020
-
-
Heinrich Schuchardt authored
CONFIG_EFI_LOADER cannot be selected for ARMv7-M CPUs. So don't check it in the Makefile. Signed-off-by:Heinrich Schuchardt <xypron.glpk@gmx.de>
-
Heinrich Schuchardt authored
The image size is checked in efi_load_pe(). Avoid checking it twice. Signed-off-by: -
Heinrich Schuchardt authored
* Eliminate superfluous enum value EFI_TABLE_END. * Use correct variable type for the memory type. * Check validity of memory type. * Make efi_build_mem_table static. Signed-off-by: -
Heinrich Schuchardt authored
Currently if the bootefi command fails due to missing authentication, the user gets no feedback. Write a log message 'Image not authenticated' if LoadImage() fails due to missing authentication. Signed-off-by: -
Heinrich Schuchardt authored
Use log_err() for error messages. Replace debug() by EFI_PRINT(). Signed-off-by: -
Heinrich Schuchardt authored
Write log messages when booting via the bootefi command to allow tracking on the syslog server. Example messages are Booting /snp.efi or Booting /MemoryMapped(0x0,0x4fe00000,0x35a40) Loading image failed Signed-off-by: -
Heinrich Schuchardt authored
Use log functions for error and debug messages of the file-system. Signed-off-by:
Simon Glass <sjg@chromium.org>
-
- Sep 04, 2020
-
-
https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini authored
- Fix SATA issue on Armada 3720 - Enable more SPI NOR chips in espressobin defconfig
-
Enable support of ISSI SPI flashes found on EspressoBIN boards Change-Id: I6de61c48f108fb4f410f321b9db45887d23212e5 Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61455 Tested-by:
iSoC Platform CI <ykjenk@marvell.com> Reviewed-by:
Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by:
Stefan Chulski <stefanc@marvell.com> Reviewed-by:
Stefan Roese <sr@denx.de>
-
Include support for CONFIG_SPI_FLASH_GIGADEVICE for supporting newly produces EspressoBin boards (v7) Change-Id: I5d4b972cbe2ee5a9d52ce9908794ad4e1b59ee3b Signed-off-by:
Igal Liberman <igall@marvell.com> Reviewed-by:
-
- This patch moves sata phy powerup from dedicate phy to compphy and adds invert option for sata powerup routine. Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90 Signed-off-by:
zachary <zhangzg@marvell.com> Signed-off-by:
Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53601 Reviewed-by:
Andre Heider <a.heider@gmail.com> Tested-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
-
- Sep 03, 2020
-
-
-
-
-
Chee Hong Ang authored
Instead of querying SDM for FPGA configuration status through mailbox messages, U-Boot now checks System Manager's FPGA Config status register for FPGA configuration status before resetting bridge. Signed-off-by:
Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by:
Ley Foon Tan <ley.foon.tan@intel.com>
-
