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  1. Feb 26, 2021
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    • Tom Rini's avatar
      Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze · cbe607b9
      Tom Rini authored
      Xilinx changes for v2021.04-rc3
      
      qspi:
      - Support for dual/quad mode
      - Fix speed handling
      
      clk:
      - Add clock enable function for zynq/zynqmp/versal
      
      gem:
      - Enable clock for Versal
      - Fix error path
      - Fix mdio deregistration path
      
      fpga:
      - Fix buffer alignment for ZynqMP
      
      xilinx:
      - Fix reset reason clearing in ZynqMP
      - Show silicon version in SPL for Zynq/ZynqMP
      - Fix DTB selection for ZynqMP
      - Rename zc1275 to zcu1275 to match DT name
      cbe607b9
    • Brandon Maier's avatar
      spi: zynqmp_gqspi: fix set_speed bug on multiple runs · d9aa19ef
      Brandon Maier authored
      
      If zynqmp_qspi_set_speed() is called multiple times with the same speed,
      then on the second call it will skip recalculating the baud_rate_val as
      it assumes the speed is already configured correctly. But it will still
      write the baud_rate_val to the configuration register and call
      zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the
      baud_rate_val, it will use the initial value of 0 . This causes the
      driver to run at maximum speed which for many spi flashes is too fast and
      causes data corruption.
      
      Instead only write out a new baud_rate_val if we have calculated the
      correct baud_rate_val.
      
      This opens up another issue with the "if (speed == 0)", we don't save
      off the new plat->speed_hz value when setting the baud rate on the
      speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and
      have speed==0 just use the same calculation as a normal speed. That will
      cause the baud_rate_val to use the slowest speed possible, which is the
      safest option.
      
      Signed-off-by: default avatarBrandon Maier <brandon.maier@rockwellcollins.com>
      CC: jagan@amarulasolutions.com
      CC: michal.simek@xilinx.com
      CC: Ashok Reddy Soma <ashokred@xilinx.com>
      Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
      d9aa19ef
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