This contributor prefers not to receive mails authored 3 years ago and Stefan Roese committed 3 years ago

There is no maintainer entry for serial_mvebu_a3700.c. Add entry with Pali
and Stefan as maintainers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>

This contributor prefers not to receive mails authored 3 years ago and Stefan Roese committed 3 years ago

There is no maintainer entry for pci-aardvark.c. Add entry for
pci-aardvark.c and pci_mvebu.c with Pali and Stefan as maintainers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>

Stefan Eichenberger authored 3 years ago and Stefan Roese committed 3 years ago

This is a backport from Marvell U-Boot:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell


commit 381d029e7a ("fix: serdes: a38x, a39x: Improve USB3 electrical
configuration")

Improves electrical USB3 receiver jitter tolerance test:

- De-Emphasize force, in functional mode the transmitter should always
have 3.5db de-emphasize, so we are forcing it.

- After forcing De-Emphasize, choose 3.5db (After forcing, default is
6dB so need to change it to 3.5dB).

- Align90 set to 0x58 - this is the sample point in the receiver, after
the clock is recovered this sampler samples at the chosen value, usually
it is supposed to be 0x60(which is the center of the eye), but sometimes
after adding jitter and ISI the center of the eye can move slightly and
the sample point is not necessarily the exact center, and after
optimization (searching the middle of the eye manually) it was seen that
the center of the eye is actually 0x58 and not 0x60.

- FFE Res and FFE Cap set to 0xE & 0xF respectively: improves this
settings is adequate according to how the USB3 spec defines the
interconnect, thus improves USB3 jitter tolerance settings.

- Change the resolution of the DFE to 0x3 which is 6mV(highest
resolution) , this avoids the DFE to saturate and cease to work.

- HPF set to 0x3 which is 5Khz high pass filter, the function of the HPF
is to filter the low frequency patterns(below 5Khz) to make sure that
the signal is not a noise, the setting before was 0x1(205Khz), and the
change came since the USB3 CP0 pattern, that is used in the USB3 jitter
tolerance testing, is similar to PRBS15, which has 2^15=32768bits which
is 32768*200ps (200ps is one Unit interval in USB3(5Gbps)) = 6.5us,
which is in frequency terms: 152Khz. since the PRBS15 is a random
pattern and can theoretically have once in a while a pattern that will
be at frequency of 152Khz, hence the previous setting (205khz HPF) can
possibly filter this pattern which can cause to an error in the
receiver, thus this change to avoid such scenarios.

Signed-off-by: Stefan Eichenberger <eichest@gmail.com>
Signed-off-by: René Straub <rene.straub@netmodule.com>
Reviewed-by: Stefan Roese <sr@denx.de>

Stefan Eichenberger authored 3 years ago and Stefan Roese committed 3 years ago

The electrical serdes configuration for USB3 expects an array as data
argument. For USB3 the second value is used (see data_arr_idx = USB3 =
1). However, because only one value is inside the array mv_seq_exec is
accessing an invalid element and the serdes is configured wrongly.

This wrong initialization is leading to an unreliable detection
mechanism for some USB3 devices. We were able to reproduce the issue
regularly with an LTE modem from Sierra Wireless (SM7455) where it was
not detected as USB3 device in 1/3 of all tests.

This commit fixes the issue by setting data_arr_idx to 0. This is the
same value as the original U-Boot from Marvell is using. There it is
called FIRST_CELL which is a define for 0.
See: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell


commit 56f963ce4c ("fix: serdes: a38x, a39x: Fix USB3 serdes DB
initialization")

Signed-off-by: Stefan Eichenberger <eichest@gmail.com>
Signed-off-by: René Straub <rene.straub@netmodule.com>
Reviewed-by: Stefan Roese <sr@denx.de>

Marek Behún authored 3 years ago and Stefan Roese committed 3 years ago

Move Turris MOX specific remove_disabled_nodes() to fdt_support with
name fdt_delete_disabled_nodes(), so that others can potentially use it.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

Marek Behún authored 3 years ago and Stefan Roese committed 3 years ago

The pre-relocation board topology reading in board_fix_fdt() is
unstable: sometimes wrong data are read from the SPI bus.

This is due to wrong order of SPI bus configuration instructions: we
first need to set the pins to SPI mode, and only after that configure
the bus.

Also add a 1ms delay before enabling chip-select, so that the clock pin
is high for some time before reading the bus.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

This contributor prefers not to receive mails authored 3 years ago and Stefan Roese committed 3 years ago

Convert A3720 common PHY driver to official DT bindings.

This puts us closer to be able to synchronize A3720 device-trees with
those from Linux.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Marcin Wojtas <mw@semihalf.com>
Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Stefan Roese <sr@denx.de>

This contributor prefers not to receive mails authored 3 years ago and Stefan Roese committed 3 years ago

Enable eth1 node in U-Boot's device-tree if a network module (SFP, Topaz
or Peridot) is detected.

This is required for proper detection of eth1 comphy in a3700 comphy
driver by the following patches.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

Marek Behún authored 3 years ago and Stefan Roese committed 3 years ago

It is better to find DT nodes by compatible strings or aliases instead
of path.

There were issues with Linux some DTBs having different names of some
nodes, e.g.
  internal-regs
instead of
  internal-regs@d0000000

This should be a generic fix for such issues.

Also since fdt_support now contains needed functions, we can drop our
own implementations.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

Marek Behún authored 3 years ago and Stefan Roese committed 3 years ago

Add functions
  fdt_node_offset_by_pathf(),
  fdt_create_phandle_by_pathf(),
  fdt_set_status_by_pathf()
to get node offset, get/create node phandle and set status for node
given by path/alias formatted with sprintf.

Add functions
  fdt_create_phandle_by_compatible(),
  fdt_set_status_by_compatible()
to get/create node phandle and set status for first node given by
compatible.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

Marek Behún authored 3 years ago and Stefan Roese committed 3 years ago

This function does not necessarily create a new phandle. If a phandle
exists, no new phandle is created.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

Marek Behún authored 3 years ago and Stefan Roese committed 3 years ago

Since no one uses this feature and I am not aware of any parsers of this
in Linux, remove it.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Marek Behún authored 3 years ago and Stefan Roese committed 3 years ago

Commit f0921f50 ("fdt: Sync up to the latest libfdt") introduced
fdt_generate_phandle() in libfdt, making fdt_alloc_phandle() obsolete in
fdt_support.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: "hui.song" <hui.song_1@nxp.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Marek Behún authored 3 years ago and Stefan Roese committed 3 years ago

Replace fdt_alloc_phandle() with subsequent fdt_set_phandle() by
fdt_create_phandle().

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>

This contributor prefers not to receive mails authored 3 years ago and Stefan Roese committed 3 years ago

The macro __constant_cpu_to_be32() uses ___constant_swab32(), which for
some reason is not defined and causes the following error during
compilation:

  include/linux/byteorder/little_endian.h:28:52: warning:
    implicit declaration of function ‘___constant_swab32’;
    did you mean ‘__builtin_bswap32’? [-Wimplicit-function-declaration]
   #define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x)))

Declare all ___constant_swabXX() macros.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

Now with DM I2C support enabled we need to describe the I2C busses and
devices in the DT.

Signed-off-by: Stefan Roese <sr@denx.de>

No functional change intended. This patch switches from the legacy I2C
API to the DM I2C API, so that this code can be used with DM I2C
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>

This function is not referenced in mainline U-Boot. Let's remove now.

Signed-off-by: Stefan Roese <sr@denx.de>

After all Armada XP boards have been switched over from legacy I2C
support to DM I2C, let's now also convert this serdes code to use
the DM I2C API.

Signed-off-by: Stefan Roese <sr@denx.de>

No functional change intended. This patch switches from the legacy I2C
API to the DM I2C API, so that this code can be used with DM I2C
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>

Move to the DM I2C version, so that this board will not get dropped from
mainline.

Signed-off-by: Stefan Roese <sr@denx.de>

Move to the DM I2C version, so that this board will not get dropped from
mainline.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>

Move to the DM I2C version, so that this board will not get dropped from
mainline.

Signed-off-by: Stefan Roese <sr@denx.de>

Move to the DM I2C version, so that this board will not get dropped from
mainline.

Signed-off-by: Stefan Roese <sr@denx.de>

binman support for ATF FIP
fdtgrep fixes for empty devicetree

In strange cases it is possible for fdtgrep to find nothing to output.
Typically this means that the resulting SPL device tree is not going to
allow anything to boot, but at present the tree is actually invalid,
since it only has an END tag in the struct region.

The FDT spec requires at least a root node. So add a special case to
include at least this, if the FDT_REG_SUPERNODES flag is set.

This ensures that grepping an empty tree still produces a valid tree.

Also add comments to the enum since it is not completely obvious from
the names now.

The typical symptom of this problem is a message from binman:

   pylibfdt error -11: FDT_ERR_BADSTRUCTURE

Signed-off-by: Simon Glass <sjg@chromium.org>

When outputting a devicetree we should not align the struct section to a
16-byte boundary. The normal position is fine, which is 8-byte aligned.

This avoids leaving adding 8 extra zero bytes in the output tree in the
case where the reserved section is empty (i.e has 16 zero bytes).

Signed-off-by: Simon Glass <sjg@chromium.org>

Ivan Mikhaylov authored 3 years ago and Simon Glass committed 3 years ago

Add the 'missing-msg' for blobs for more detailed output on missing system
firmware and SEBoot blobs.

Signed-off-by: Ivan Mikhaylov <ivan.mikhaylov@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix minor typos:
Signed-off-by: Simon Glass <sjg@chromium.org>

Andy Shevchenko authored 3 years ago and Simon Glass committed 3 years ago

Instead of joining hard coded '..' to the run-time path of the executable,
take just a dirname out of it. Besides that, use $(srctree) where it makes
sense.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Andy Shevchenko authored 3 years ago and Simon Glass committed 3 years ago

Importing libraries in Python caches the bytecode by default.
Since we run scripts in source tree it ignores the current directory
settings, which is $(srctree), and creates cache just in the middle
of the source tree. Move cache to the current directory.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

This converts the following to Kconfig:
   CONFIG_PHYSMEM

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Sean Anderson <seanga2@gmail.com>

This format is used in firmware binaries so we may as well supported it.

With this patch binman supports creating, listing and updating FIPs, as
well as extracting files from one, provided that an FDTMAP is also present
somewhere in the image.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add support for this format which is used by ARM Trusted Firmware to find
firmware binaries to load.

FIP is like a simpler version of FMAP but uses a UUID instead of a name,
for each entry.

It supports reading a FIP, writing a FIP and parsing the ATF source code
to get a list of supported UUIDs.

Signed-off-by: Simon Glass <sjg@chromium.org>

First set of u-boot-at91 features for the 2022.04 cycle:

This feature set includes : support for the new QSPI hardware on
sama7g5, small fixes on sam9x60 and sama7g5, some additions of commands
and PIO controller on sam9x60/sam9x60ek.

New SoC's of AT91 family with ARM-9 core includes a regular timer and a 64-bit
timer.This patch adds a compile time option to the Makefile such that the old
timer driver is chosen and compiled as default if none of timer configuration
options are explicitly defined in the board configs.

Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>

The alternate function of PD20 is 4 as per the datasheet of
sama7g5 and not 5 as defined earlier.

Fixes: 558378a4 ("ARM: mach-at91: add support for new SoC sama7g5")
Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>

QSPI0 has a MX66LM1G45G SPI NOR flash connected.
Enable the controller and describe the flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

sama7g5 embedds an OSPI and a QSPI controller:
1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
   and OctaFlash Protocols Supported.
2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

sama7g5 QSPI has:
1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to
   200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported
2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to
   90 MHz DDR/133 MHz SDR

The QSPI controller of SAMA7G5 uses different clock domains, hence extra
synchronization operations must be performed before accessing some
registers. Differentiate between the versions of the IP using has_gclk.
Differentiate between QSPI0 and QSPI1 with has_octal.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

binman refactoring to improve section handling
bloblist - allow it to be allocated
sandbox config-header cleanup

# gpg: Signature made Sun 05 Dec 2021 10:14:24 PM EST
# gpg:                using RSA key B25C0022AF86A7CC1655B6277F173A3E9008ADE6
# gpg:                issuer "sjg@chromium.org"
# gpg: Good signature from "Simon Glass <sjg@chromium.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B25C 0022 AF86 A7CC 1655  B627 7F17 3A3E 9008 ADE6