- Feb 05, 2022
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With the current configuration provided in mxsimage{-spl}.mx28.cfg the size of SPL binary has been constrained to 32 KiB, due to "LOAD IVT" command with 0x8000 offset. The problem was that, the imx28 ROM takes the u-boot.sb and then extracts from it the IVT header and places it on the 0x8000 OCRAM offset overwriting any valid (i.e. loaded from eMMC or SPI-NOR) SPL code. This bug was unnoticed as the overwrite size was just 32 bytes, so the probability that some important code is altered was low. However, in the XEA board (where the SPL size is ~39KiB), the overwritten data was `(struct dm_spi_ops *) 0x800c <mxs_spi_ops>`, which is used during the boot process. As a result the SPL execution code hanged with "undefined instruction" abort as callbacks (with wrong addresses) from it were called. The fix is to change the OCRAM's offset where IVT is loaded to 0xE000, so the SPL can grow up to ~57KiB (the maximal size of OCRAM memory available is 0xE3FC). Signed-off-by:Lukasz Majewski <lukma@denx.de>
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According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may have the ESAI_TX0 functionality, not ESAI_T0. Also, NXP's i.MX Config Tools 10.0 generates dtsi with the MX6ULL_PAD_CSI_DATA07__ESAI_TX0 naming, so fix it accordingly. There are no devicetree users in mainline that use the old name, so just remove the old entry. Fixes: f8ca22b8 ("arm: dts: imx6ull: add pinctrl defines") Reported-by:
George Makarov <georgemakarov1@gmail.com> Signed-off-by:
Fabio Estevam <festevam@gmail.com> Acked-by:
Peng Fan <peng.fan@nxp.com>
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Use imx6_src_get_boot_mode() instead of manually reading SBMR1. The existing function has proper handling for software overrides of the bootdevice which can happen, for example, when booting from an alternate source using `bmode`. Signed-off-by:
Harald Seiler <hws@denx.de>
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The PDK2 board is capable of running both 100M and 1G ethernet. However, the i.MX6 has only one ethernet MAC, so it is possible to configure either 100M or 1G Ethernet. In case of 100M option, the PHY is on the SoM and the signals are routed to a RJ45 port. For 1G the PHY is on the PDK2 board with another RJ45 port. 100M and 1G ethernet use different signal pins from the i.MX6, but share the MDIO bus. This SoM board combination is used to demonstrate how to enable 1G ethernet configuration. Signed-off-by:
Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com> Cc: Stefano Babic <sbabic@denx.de>
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If `sb_load_cmdfile()` fails to open the configuration file it will jump to error handling where the code will try to `fclose()` the FILE pointer which is NULL causing `mkimage` to segfault. This patch removes the label for error handling and instead returns immediately which skips the `fclose()` and prevents the segfault. The errno is also described in the error message to guide users. Signed-off-by:
Mattias Hansson <hansson.mattias@gmail.com> Reviewed-by:
Wolfgang Denk <wd@denx.de>
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Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for: - 1GiB DDR4 RAM - 16 GiB eMMC - SD card - Gigabit ethernet - USBOTG1 peripheral - fastboot Signed-off-by:
Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
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The FXL6408 GPIO expander manages critical devices, including on-module USB hub. Configure the expander to switch the USB hub into bypass mode, allowing to use on-carrier-board USB hub. Signed-off-by:
Oleksandr Suvorov <cryosay@gmail.com> Signed-off-by:
Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
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Initial support for Fairchild's 8 bit I2C gpio expander FXL6408. The CONFIG_FXL6408_GPIO define enables support for such devices. Based on: https://patchwork.kernel.org/patch/9148419/ Signed-off-by:
Simon Glass <sjg@chromium.org> Tested-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by:
Heiko Schocher <hs@denx.de> Signed-off-by:
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Previously these two options are called CONFIG_SPL_MMC_SUPPORT and CONFIG_SPL_SERIAL_SUPPORT. During the transition they are removed by accident. Thus adding them back. Signed-off-by:
Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by:
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The value of cnt is overwritten without being used. Signed-off-by:
Haolin Li <li.haolin@qq.com> Reviewed-by:
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Extension boards can be added to Compulab's iot-gate-imx8mm. We implement extension board manager for detecting the extension boards. Signed-off-by:
Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by:
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add the following overlays: - IED extension board - CAN/TPM/ADC extension board on IED board. Signed-off-by:
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After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by:
Ye Li <ye.li@nxp.com> Signed-off-by:
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On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by:
Jacky Bai <ping.bai@nxp.com> Signed-off-by:
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Obatin the SoC current temperature in print_cpuinfo(). Reviewed-by:
Alice Guo <alice.guo@nxp.com> Signed-off-by:
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The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by:
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This patch implements enable_adc1_clk() to enable or disable the ADC1 clock on i.MX8ULP. Reviewed-by:
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Get the MAC address from fuse bank5 word 3 and 4. It has MSB first at lowest address, so have a reverse order with other iMX used in mac.c Reviewed-by:
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When LPAV is allocated to RTD, the LPAV won't be reset. So we have to reset DCNano and MIPI DSI in u-boot before enabling the drivers Reviewed-by:
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The LPAV is not allocated to APD when dual boot, so LPAV won't reset when APD is reset. We have to explicitly reset the DDR, otherwise its initialization will fail. Reviewed-by:
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8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0 LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision. A0.2 will fix the issue in ROM. But A0.1 we have to workaround it in SPL by setting LPOSCCTRL BIASCURRENT again. Reviewed-by:
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Remove the freescale vendor name from CPU revision print to align with other i.MX platforms Reviewed-by:
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The setting does not have effect because we should set it after power on the PS16 for NIC AV. So move it after upower_init which has powered on all PS Reviewed-by:
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To avoid DCNANO underrun issue on high loading test, set its read Qos on NIC_LPAV to highest Reviewed-by:
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The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and backlight. However the LPI2C0 and TPM0 are M33 resources, in this patch we simply access them, but this is a temporary solution. We will modify it when M33 FW changes to set MIPI DSI panel as default path and enable backlight after reset. Signed-off-by:
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For singel boot, set flexspi0 mem to be accessed by A35 Signed-off-by:
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Add the DSI clock enable and disable with PCC reset used. Add the LCD pixel clock calculation and configuration for DCNano Signed-off-by:
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Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC. Signed-off-by:
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Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not able to receive interrupts from the modules. Reviewed-by:
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When single boot, assign AP domain as the master domain of the LPAV. Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI eDMA channel and eDMA request to APD Signed-off-by:
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S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC is allowed by all masters. Current S400 has issue if the XRDC has released to A35, then A35 reset will fail in ROM due to S400 fails to get XRDC. So temp work around is checking the DBD_EN, if it is not fused, we don't need to call release XRDC or TRDC. Signed-off-by:
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Change boot device logic to also allow environment stored in fat and in ext4 when booting from SD or from eMMC. As the boot device check for SD and for eMMC was depending on ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location to use IS_ENABLED instead for all modes, returning NOWHERE when no valid mode is found. Signed-off-by:
Ricardo Salveti <ricardo@foundries.io> Reviewed-by:
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Correct printf format for unsigned long long is %llx and not %llxx. Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
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The imx28 uses following voltage supplies hierarchy: VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM \-----> VDDD One shall first enable DCDC on the parent source (VDDIO) and then follow with its children. Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by:
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Fix the invalid gw7902 M2_RST# gpio pinmux. Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Reviewed-by:
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Add EA iMX7ULP COM board support for building SPL. Signed-off-by:
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Force selecting features present in SoC i.MX7ULP. Signed-off-by:
Igor Opaniuk <igor.opaniuk@foundries.io>
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Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK, MXC_UART_CLK and MXC_QSPI_CLK. At least for the I2C clock the missing support leads to a wrong configured I2C frequency. The expected value is 100kHz but the resulting value is about 1MHz. Signed-off-by:
Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by:
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Use the complete 512kb (4 blocks) nand partition reserved for u-boot environment instead of just the first block, this allows the module to have a working environment even if 3 blocks are bad. Signed-off-by:Francesco Dolcini <francesco.dolcini@toradex.com>
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- Feb 04, 2022
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https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini authored
This is the promised second part of the sunxi PR for 2022.04, albeit technially outside of the merge window. We were working on this full steam since the beginning of the year, and it deserves to be merged, I think. The main attraction is support for the F1C100s SoC, which sports a venerable ARM926 core. Support for this SoC and the LicheePi Nano board has been in Linux for years, and U-Boot patches were posted mid last year already. The new SoC using ARMv5 also means that the bulk of the new code should not touch any existing boards, although we did some refactorings first, of course, which actually cleans up some existing sunxi code. Compile tested for all 160 sunxi boards, and briefly tested on BananaPi M1, OrangePi Zero, Pine64 and Pine-H64. Tested by others on their boards, including F1C100s and F1C200s devices.
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