- Jul 14, 2021
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Nomadik GPIO is a fairly simple GPIO module used in the ST-Ericsson Ux500 SoCs (and some older Nomadik SoCs). It uses registers where each GPIO is represented as a single bit, plus "set" and "clear" registers that allow updating the state without having to read the existing state. The driver implements support for it for use together with DM_GPIO and the existing ste-dbx5x0.dtsi device tree. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org>
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The original U-Boot port for the ST-Ericsson U8500 SoC was dropped in commit 68282f55 ("arm: Remove unused ST-Ericsson u8500 arch"). Most of the drivers related to the old port were removed, but the db8500_gpio.c driver was forgotten for some reason. There is no way to select it and it does not compile anymore because of missing headers, so let's just remove it. The new port for U8500 introduced in commit 689088f9 ("arm: Add support for ST-Ericsson U8500 SoC") fully embraces the new Driver Model and device trees where possible, so this is preparation to add a new, simplified GPIO driver based on DM_GPIO. Signed-off-by:
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This information will be maintained in the device tree instead. Signed-off-by:Anders Dellien <anders.dellien@arm.com>
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- Jul 13, 2021
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https://source.denx.de/u-boot/custodians/u-boot-efiTom Rini authored
Pull request for efi-2021-10-rc1 Documentation * fix typo in signature.txt UEFI * provide file attributes in EFI_FILE_PROTOCOL.Read() * various capsule update fixes
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- Jul 12, 2021
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Fix find_boot_device() to set bootdev_root if it finds the bootdev from BootNext. Currently it sets the bootdev_root only when it finds bootdev from BootOrder. Fixes: c74cd8bd ("efi_loader: capsule: add capsule_on_disk support") Signed-off-by:
Masami Hiramatsu <masami.hiramatsu@linaro.org> Accked-by:
Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by:
Heinrich Schuchardt <xypron.glpk@gmx.de>
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Heinrich Schuchardt authored
If multiple capsules are applied, the FMP drivers for the individual capsules can expect the value of CapsuleLast to be accurate. Hence CapsuleLast must be updated after each capsule. Signed-off-by: -
Heinrich Schuchardt authored
efi_set_variable() should be called with EFI_CALL(). Use efi_set_variable_int() instead. Signed-off-by: -
Heinrich Schuchardt authored
* Use log category LOGC_EFI. This allows to remove 'EFI:' prefixes in messages. * Rephrase some of the messages. Signed-off-by: -
Heinrich Schuchardt authored
When reading a directory using EFI_FILE_PROTOCOL.Read() provide file attributes and timestamps. Signed-off-by: -
Heinrich Schuchardt authored
We should avoid #ifdef in C modules. Unused functions are eliminated by the linker. Signed-off-by: -
Heinrich Schuchardt authored
When reading a directory in the UEFI file system we have to return file attributes and timestamps. Copy this data to the directory entry structure. Signed-off-by: -
Fix value fields in signature nodes. Signed-off-by:
Thomas Perrot <thomas.perrot@bootlin.com> Reviewed-by:
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- Jul 10, 2021
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https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini authored
Aside from the usual fixes and updates one visible change is the MMC update, which fixes some lingering bugs and gives a decent speed increase on some boards (9->19 MB/s on H6, 21->43 MB/s on A64 eMMC). I am keeping an watchful eye on bug reports here, to spot any correctness regressions. Another change is finally the enablement of the first USB host port on many boards without micro-USB (data) sockets, like the Pine64 family. That doubles the number of usable USB ports from 1 to 2 on those boards. Some smaller fixes, 4GB DRAM support (on the H616) and a new board (ZeroPi) conclude this first round of changes. Compile-tested for all 157 sunxi boards, boot-tested on Pine H64, Pine64-LTS, OrangePi Zero 2 and BananaPi M2 Berry. Summary: - DT update for H3/H5/H6 - Enable first USB port on boards without micro-USB - ZeroPi board support - 4GB DRAM support for H616 boards - MMC fixes and speed improvement - some fixes
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André Przywara authored
At the moment the Allwinner MMC driver parses the bus-width and non-removable DT properties itself, in the probe() routine. There is actually a generic function provided by the MMC framework doing this job, also it parses more generic properties like broken-cd and advanced transfer modes. Drop our own code and call mmc_of_parse() instead, to get all new features for free. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
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André Przywara authored
To avoid the complexity of DMA operations (with chained descriptors), we use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us to drain or fill the MMC data buffer FIFO very easily. However those MMIO accesses are somewhat costly, so this limits our MMC performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6 (partly due to the lower AHB1 frequency). As it turns out we read the FIFO status register after *every* word we read or write, which effectively doubles the number of MMIO accesses, thus effectively more than halving our performance. To avoid this overhead, we can make use of the FIFO level bits, which are in the very same FIFO status registers. So for a read request, we now can collect as many words as the FIFO level originally indicated, and only then need to update the status register. We don't know for sure the size of the FIFO (and it seems to differ across SoCs anyway), so writing is more fragile, which is why we still use the old method for that. If we find a minimum FIFO size available on all SoCs, we could use that, in a later optimisation. This patch increases the eMMC read speed on a Pine64-LTS from about 22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s we now reach the practical limit for 3.3V SD cards. On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s. Signed-off-by: -
André Przywara authored
Newer SoCs have a self calibration feature, which avoids us writing hard coded phase delay values into the controller. Consolidate the code by avoiding unnecessary #ifdefs, and also enabling the feature for all those newer SoCs. Signed-off-by: -
André Przywara authored
All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature the so called "new timing mode", so enable this in Kconfig for those SoCs. Signed-off-by: -
André Przywara authored
Among the SoCs using the "new timing mode", only the A83T needs to explicitly switch to that mode. By just defining the symbol for that one odd A83T bit to 0 for any other SoCs, we can always OR that in, and save the confusing nested #ifdefs. Clean up the also confusing new_mode setting on the way. Signed-off-by:
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André Przywara authored
Most Allwinner SoCs which use the so called "new timing mode" in their MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their parent input clock. This is interestingly enough compensated by a hidden "by 2" post-divider in the mod clock, so the divider and actual output rate stay the same. Even though for the H6 and H616 (but only for them!) we use the doubled input clock for the divider computation, we never accounted for the implicit post-divider, so the clock was only half the speed on those SoCs. This didn't really matter so far, as our slow MMIO routine limits the transfer speed anyway, but we will fix this soon. Clean up the code around that selection, to always use the normal PLL6 (PERIPH0(1x)) clock as an input. As the rate and divider are the same, that makes no difference. Explain the hardware differences in a comment. Signed-off-by: -
André Przywara authored
When enabling PHYS_64BIT on 32-bit platforms, we get two warnings about pointer casts in sunxi_mmc.c. Those are related to MMIO addresses, which are always below 1GB on all Allwinner SoCs, so there is no problem with anything having more than 32 bits. Add the proper casts to make it compile cleanly. Signed-off-by:
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André Przywara authored
The delay and bus-width setup are slightly different across the Allwinner SoC generations, and we covered this so far with some preprocessor conditionals. Use the more readable IS_ENABLE() instead. Signed-off-by:
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André Przywara authored
The H616 is our first supported Allwinner SoC which goes beyond the 4GB address space "barrier", by having more than 32 address bits. Lift the preliminary 3GB DRAM limit for the H616, and update the page table setup on the way, to actually map that last GB as well. As not all devices are actually capable of dealing with more than 32 bits (the DMA in the EMAC for instance), we also limit U-Boot's own DRAM usage to 4GB on the way. Signed-off-by: -
André Przywara authored
We hardcode the pinctrl setting for the MMC controllers in boards.c, since we need them also in the SPL, where there is no DT yet. Add the respective setting for the H616 SoC, to enable eMMC on boards with this SoC as well. Also to make diagnosing this problem easier, print a warning if a board tries to setup MMC2 pins without a respective SoC setting being defined. Signed-off-by: -
ZeroPi is a new board of high performance with low cost designed by FriendlyElec., using the Allwinner H3 SOC. ZeroPi features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 256MB/512MB DDR3 RAM - microsd slot - 10/100/1000Mbps Ethernet - Debug Serial Port - DC 5V/2A power-supply Signed-off-by:
Yu-Tung Chang <mtwget@gmail.com> Reviewed-by:
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OrangePi PC2 board has DRAM with ODT, so enable it. H5 SoC is also connected to voltage regulator. It's default value is reasonable at reset, but might be too low when rebooting with a lower voltage programmed. In order to avoid instability, enable driver for it and set it to appropriate voltage. Signed-off-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by:
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André Przywara authored
Most clock factors and dividers in the H6 PLLs use a "+1 encoding", which we were missing on two occasions. This fixes the MMC clock setup on the H6, which could be slightly off due to the wrong parent frequency: mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000 Also the CPU frequency (PLL1) was a tad too high before. For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code itself, not in the bit field macro. Move this there to be aligned with what the other SoCs and other PLLs do. Signed-off-by:
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Recent Allwinner platforms (starting with the H3) only use the MUSB controller for peripheral mode and use HCI for host mode. As a result, extra steps need to be taken to properly route USB signals to one or the other. More precisely, the following is required: * Routing the pins to either HCI/MUSB (controlled by PHY); * Enabling USB PHY passby in HCI mode (controlled by PMU). The current code will enable passby for each PHY and reroute PHY0 to MUSB, which is inconsistent and results in broken USB peripheral support. Passby on PHY0 must only be enabled when we want to use HCI. Since host/device mode detection is not available from the PHY code and because U-Boot does not support changing the mode dynamically anyway, we can just mux the controller to MUSB if it is enabled and mux it to HCI otherwise. This fixes USB peripheral support for platforms with PHY0 dual-route, especially H3/H5 and V3s. Signed-off-by:
Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by:
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André Przywara authored
Update the H3 DT files from the Linux 5.12 release. The changes update some boards, and don't affect U-Boot, but fix Gigabit Ethernet when this DT is passed on to the Linux kernel. Signed-off-by: -
André Przywara authored
Update the H5 DT files from the Linux 5.12 release. The changes don't affect U-Boot at all, but fix Gigabit Ethernet when this DT is passed on to the Linux kernel. It also introduces DVFS. This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes that are of no concern to U-Boot. Signed-off-by: -
André Przywara authored
Update the H6 DT files from the Linux 5.12 release. The changes are minimal (many LED node renames), but also help to enable USB port 0 in U-Boot (later), enable the RSB device (not yet used in U-Boot), and also introduce an MMC frequency limit. Signed-off-by:
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- Jul 09, 2021
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Tom Rini authored
- Assorted ARM platform updates
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https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini authored
- Support higher baudrates on Armada 3720 UART (Pali & Marek) - OcteonTX: do not require cavium BDK node to be present (Tim)
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Tom Rini authored
As seen with clang-12: warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK As we indeed use ENTRY and then declare the function weak manually. Use the WEAK declarative from <linux/linkage.h> instead. Signed-off-by:Tom Rini <trini@konsulko.com>
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On arm64, board info is not applicable and kernel command line patched into the DT, so the LMB reservation here makes no sense anymore. On legacy arm32, this might still be necessary on systems which do not use DT or use legacy ATAGS. Disable this LMB reservation on arm64. This also permits Linux DT to specify reserved memory node at address close to the end of DRAM bank, i.e. overlaping with U-Boot location. Since after boot, U-Boot will be no more, this is OK. Signed-off-by:Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Hai Pham <hai.pham.ud@renesas.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com>
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Fix following compilation issue when SYS_DCACHE_OFF is enable: drivers/misc/scmi_agent.c:128: undefined reference to `mmu_set_region_dcache_behaviour' when SYS_DCACHE_OFF is enable, mmu_set_region_dcache_behaviour() must be defined. Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by:
Patrick Delaunay <patrick.delaunay@foss.st.com> -
On implementations that support VHE, the layout of the CPTR_EL2 register depends on whether HCR_EL2.E2H is set. If the bit is set, CPTR_EL2 uses the same layout as CPACR_EL1 and can in fact be accessed through that register. In that case, jump to the EL1 code to enable access to the FP/SIMD registers. This allows U-Boot to run on systems that pass control to U-Boot in EL2 with EL2 Host mode enabled such as machines using Apple's M1 SoC. Signed-off-by:
Mark Kettenis <kettenis@openbsd.org> Acked-by:
Marc Zyngier <maz@kernel.org>
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- Jul 08, 2021
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The cavium,bdk node is a non-standard dt node used by the BDK and therefore it is removed from the dt before booting Linux. Do not require this node to exist as it won't for standard dt's. Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Reviewed-by:
Stefan Roese <sr@denx.de>
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Extend CONFIG_SYS_BAUDRATE_TABLE and include all standard baudrates and also nonstandard up to the 6 MBaud. U-Boot's A3720 UART driver can use baudrates from 300 Baud to 6 MBaud. This changes all A3720 boards, since all of them include either mvebu_armada-37xx.h or turris_mox.h config file. Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
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Unfortunately the UART driver in current Linux for Armada 3700 expects UART's parent clock to be XTAL and calculats baudrate divisor according to XTAL clock. Therefore we must switch back to XTAL clock before booting kernel. Implement .remove method for this driver with DM_FLAG_OS_PREPARE flag set. If current baudrate is unsuitable for XTAL clock then we do not change anything. This can only happen if the user either configured unsupported settings or knows what they are doing and has kernel patches which allow usage of non-XTAL parent clock. Signed-off-by:
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Using TBG clock as parent clock for UART allows us using higher baudrates than 230400. Turris MOX with external FT232RL USB-UART works fine up to 3 MBaud (which is maximum for this USB-UART controller), while EspressoBIN with integrated pl2303 USB-UART also works fine up to 6 MBaud. Slower baudrates with TBG as a parent clock can be achieved by increasing TBG dividers and oversampling divider. When using the slowest TBG clock, minimal working baudrate is 300. Signed-off-by:
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