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  1. Jul 14, 2021
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    • Tom Rini's avatar
      Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi · 490101a5
      Tom Rini authored
      Aside from the usual fixes and updates one visible change is the
      MMC update, which fixes some lingering bugs and gives a decent speed
      increase on some boards (9->19 MB/s on H6, 21->43 MB/s on A64 eMMC).
      I am keeping an watchful eye on bug reports here, to spot any correctness
      regressions.
      Another change is finally the enablement of the first USB host port on
      many boards without micro-USB (data) sockets, like the Pine64 family.
      That doubles the number of usable USB ports from 1 to 2 on those boards.
      
      Some smaller fixes, 4GB DRAM support (on the H616) and a new board (ZeroPi)
      conclude this first round of changes.
      
      Compile-tested for all 157 sunxi boards, boot-tested on Pine H64,
      Pine64-LTS, OrangePi Zero 2 and BananaPi M2 Berry.
      
      Summary:
      - DT update for H3/H5/H6
      - Enable first USB port on boards without micro-USB
      - ZeroPi board support
      - 4GB DRAM support for H616 boards
      - MMC fixes and speed improvement
      - some fixes
      490101a5
    • André Przywara's avatar
      mmc: sunxi: Use mmc_of_parse() · ac62dadb
      André Przywara authored
      
      At the moment the Allwinner MMC driver parses the bus-width and
      non-removable DT properties itself, in the probe() routine.
      
      There is actually a generic function provided by the MMC framework doing
      this job, also it parses more generic properties like broken-cd and
      advanced transfer modes.
      
      Drop our own code and call mmc_of_parse() instead, to get all new
      features for free.
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
      ac62dadb
    • André Przywara's avatar
      mmc: sunxi: Increase MMIO FIFO read performance · 9faae545
      André Przywara authored
      
      To avoid the complexity of DMA operations (with chained descriptors), we
      use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
      to drain or fill the MMC data buffer FIFO very easily.
      
      However those MMIO accesses are somewhat costly, so this limits our MMC
      performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6
      (partly due to the lower AHB1 frequency).
      
      As it turns out we read the FIFO status register after *every* word we
      read or write, which effectively doubles the number of MMIO accesses,
      thus effectively more than halving our performance.
      
      To avoid this overhead, we can make use of the FIFO level bits, which are
      in the very same FIFO status registers.
      So for a read request, we now can collect as many words as the FIFO
      level originally indicated, and only then need to update the status
      register.
      
      We don't know for sure the size of the FIFO (and it seems to differ
      across SoCs anyway), so writing is more fragile, which is why we still
      use the old method for that. If we find a minimum FIFO size available on
      all SoCs, we could use that, in a later optimisation.
      
      This patch increases the eMMC read speed on a Pine64-LTS from about
      22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s
      we now reach the practical limit for 3.3V SD cards.
      On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s.
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      9faae545
    • André Przywara's avatar
      mmc: sunxi: Cleanup and fix self-calibration code · b5dd39c9
      André Przywara authored
      
      Newer SoCs have a self calibration feature, which avoids us writing hard
      coded phase delay values into the controller.
      
      Consolidate the code by avoiding unnecessary #ifdefs, and also enabling
      the feature for all those newer SoCs.
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      b5dd39c9
    • André Przywara's avatar
      mmc: sunxi: Enable "new timing mode" on all new SoCs · b6e3bf1e
      André Przywara authored
      
      All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature the so
      called "new timing mode", so enable this in Kconfig for those SoCs.
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      b6e3bf1e
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