André Przywara authored 4 years ago and Jagan Teki committed 4 years ago

When preparing the register value for the MDIO command register, we
start with a zeroed register, so there is no need to mask off certain
bits before setting them.
Simplify the sequence, and rename the variable to a more matching
mii_cmd on the way.

Also the open-coded time-out routine can be replaced with a much safer
and easier-to-read call to wait_for_bit_le32().

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

André Przywara authored 4 years ago and Jagan Teki committed 4 years ago

When initialising the TX DMA descriptors, we mostly chain them up,
but of course don't know about any data or its length yet.
That means they are still invalid, and the OWN bit should NOT be set
yet.

In fact when we later tell the MAC about the beginning of the chain,
and enable TX DMA in the start() routine, the MAC will start fetching
TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA
and TX_DMA_CUR_DESC registers.

Clear the owner bit, to not give the MAC the wrong illusion that it
owns the descriptors already.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

André Przywara authored 4 years ago and Jagan Teki committed 4 years ago

When phy_startup() returns with an error, because there is no link or
the user interrupted the process, we shall stop the _start() routine
and return with an error, instead of proceeding anyway.

This fixes pointless operations when there is no Ethernet cable
connected, for instance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Second set of u-boot-atmel features for 2021.01 cycle:

This feature set brings the rework of the clock tree for sam9x60 SoC.
This makes the clock tree fully compatible with Common Clock Framework
and allows full clock configuration in U-Boot. This means that the
sam9x60 boards can boot now using U-Boot.
This also includes the definitions for sam9x60 SiPs and a divisor fix
for the clock on sama7g5 SoC.

This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>

clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>

SAM9X60 SiP (System in Package) are added for SoC identification.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>

Use alphabetical order for entries in sam9x60ek-u-boot.dtsi

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Update defconfigs for using common clock framework compatible
clocks.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Use u-boot,dm-pre-reloc for slow xtal and main xtal.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Slow Xtal and Main Xtal are board specific. Add their proper
frequency to board file.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Add SAM9X60 clock support compatible with CCF.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Heap base address is computed based on SYS_INIT_SP_ADDR by
subtracting the SYS_MALLOC_F_LEN value in
board_init_f_init_reserve().

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

 - add dw-mipi-dsi phy timings and Tx escape clock configuration
 - fix pwm backlight duty cycle calculation
 - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig

Patrick Delaunay authored 4 years ago and Anatolij Gustschin committed 4 years ago

Done with:
./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Patrick Delaunay authored 4 years ago and Anatolij Gustschin committed 4 years ago

Done with:
./tools/moveconfig.py VIDEO_BMP_RLE8

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Patrick Delaunay authored 4 years ago and Anatolij Gustschin committed 4 years ago

Done with:
./tools/moveconfig.py VIDEO_BMP_GZIP

The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN
are not activated in these defconfigs:
- trats_defconfig
- s5pc210_universal_defconfig
- trats2_defconfig

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Dario Binacchi authored 4 years ago and Anatolij Gustschin committed 4 years ago

For levels equal to the maximum value, the duty cycle must be equal to
the period.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>

Dario Binacchi authored 4 years ago and Anatolij Gustschin committed 4 years ago

The description of the 'max_level' field was incorrectly assigned to the
'min_level' field.

Signed-off-by: Dario Binacchi <dariobin@libero.it>

Neil Armstrong authored 4 years ago and Anatolij Gustschin committed 4 years ago

The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Neil Armstrong authored 4 years ago and Anatolij Gustschin committed 4 years ago

The timing values for dw-dsi are often dependent on the used display and
according to Philippe Cornu will most likely also depend on the used phy
technology in the soc-specific implementation.

To solve this and allow specific implementations to define them as needed
add a new get_timing callback to phy_ops and call this from the dphy_timing
function to retrieve the necessary values for the specific mode.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

syslog_test.h is in test/log/, not include/

Fixes: 52d3df7f ("log: Allow LOG_DEBUG to always enable log output")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

- Fix Octeon SPI driver for Octeon TX2
- Fix and enhance Octeon watchdog driver
- Misc minor enhancements to Octeon TX/TX2

- Bring in the next round of dev_xxx cleanup patches.

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

Now that linux/compat.h does not define these macros, we do not need to
undefine them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

All users of these functions now include dm/device_compat.h directly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>

Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>

Necessary for dev_xxx.

Signed-off-by: Tom Rini <trini@konsulko.com>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

This driver doesn't use DM (in the correct places), so we use a device and
not a udevice. We also need to include device_compat.h

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

This was included, but was ifdef'd out. We also need dm.h for struct
udevice.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

This header is necessary for the dev_xxx macros.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Enable WDT command for Octeon TX/TX2 boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>

Suneel Garapati authored 4 years ago and Stefan Roese committed 4 years ago

This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
the WDT. With this changes, the "wdt" command is now also supported
on these platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>