- Apr 22, 2022
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Tom Rini authored
Resync all defconfig files using moveconfig.py Signed-off-by:Tom Rini <trini@konsulko.com>
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If dev_count_phandle_with_args returns 0 or another error, then pd will never have been initialized by power_domain_get_by_index. Avoid comparing against pd.dev in this situation. Fixes: 3e4fcfa4 ("power-domain: fix hang in endless loop on i.MX8") Signed-off-by:
Sean Anderson <seanga2@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-watchdogTom Rini authored
- device-tree-bindings: watchdog: document common properties (Philippe) - nuvoton: Add support for Nuvoton (Jim)
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https://gitlab.denx.de/u-boot/custodians/u-boot-imxTom Rini authored
u-boot-imx-20220422 ------------------- - Switch to DM_SERIAL - Drop MMCROOT - several cleanup CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/11815
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Reviewed-by:
Ramon Fried <rfried.dev@gmail.com> Signed-off-by:
Oleksii Titov <ootitov@gmail.com>
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When usb3-phy label is found, PHY driver is called and serdes line is initialized. This is preparation for serdes/psgtr driver to configure GT lines based on description in DT. Signed-off-by:Michal Simek <michal.simek@xilinx.com>
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Allow to disable PHY driver in SPL because it checks the CONFIG_SPL_PHY variable for SPL builds. The same change was done for usb by commit fd09c205 ("usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/"). Signed-off-by:
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ci_udc_ops and ci_ep_ops do not change their operations. Mark them as const. Signed-off-by:Adam Ford <aford173@gmail.com>
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Add watchdog controller driver for NPCM7xx/npcm8xx the wdt design of npcm750 and npcm845 is the same. so the driver can work on npcm750 and npcm845. about npcm845 wdt dtsi i will followed kernel dts name to use nuvoton,npcm750-wdt. Signed-off-by:
Jim Liu <JJLIU0@nuvoton.com> Reviewed-by:
Stefan Roese <sr@denx.de> Reviewed-by:
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Adds simple documentation about common properties for watchdog in the device tree. Signed-off-by:
Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by:
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- Apr 21, 2022
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Tom Rini authored
- Fix SPL_SYS_MALLOC_SIMPLE and non-SPL_FRAMEWORK boards (a large number of PowerPC platforms) - Remove duplication of crc16 functionality - Migrate COUNTER_FREQUENCY to CONFIG_COUNTER_FREQUENCY and have it in Kconfig
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Currently the space between kernel_addr_r and the fdt_addr_r is only 32MB. To have enough space to load kernel images bigger than 32MB change the variables to a feasible value. The new environment variables layout is based on the scheme from "include/configs/ti_armv7_common.h". The CONFIG_SYS_LOAD_ADDR value is set to 0x42000000. With that we have the same value as for the kernel_addr_r. Signed-off-by:
Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com>
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IMX_FEC_BASE is not used in these boards, so drop it. Reviewed-by:
Fabio Estevam <festevam@denx.de> Signed-off-by:
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In arch/arm/mach-imx/imx8m/soc.c there's an implementation of board_fix_fdt() introduced by commit 35bb6078. Remove the redundant one to avoid failed to build from source when enabling CONFIG_OF_BOARD_FIXUP. Signed-off-by:
Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by:
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Since COUNTER_FREQUENCY is obselete, so set cntfrq_el0 if CONFIG_COUNTER_FREQUENCY is valid Signed-off-by:
Philipp Tomsich <philipp.tomsich@vrull.eu>
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Since we have CONFIG_COUNTER_FREQUENCY enabled, no need COUNTER_FREQUENCY Signed-off-by: -
Set CONFIG_COUNTER_FREQUENCY according to COUNTER_FREQUENCY in config header file. Signed-off-by: -
Set default COUNTER_FREQUENCY according to config header file under include/configs/ i.MX6UL/ULL/7D/8QM/8QXP all has system counter frequency run at 8MHz, so set default value for them. SUNXI/EXYNOS/ROCKCHIP_RK3128/ROCKCHIP_RK3288/ROCKCHIP_RK322X/ROCKCHIP_RK3036 at 24MHz. ARCH_LX2160A at 25MHz ARCH_ZYNQMP at 100MHz
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Make COUNTER_FREQUENCY usable to armv8 and armv7-a, not limited to versal. And update help message. Signed-off-by: -
Since versal has CONFIG_COUNTER_FREQUENCY, so use it. And COUNTER_FREQUENCY will be dropped. Signed-off-by:
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ATSHA204A uses bit-reversed checksum of standard CRC-16 with polynomial x^16 + x^15 + x^2 + 1. This ATSHA204A specific checksum can be calculated just by using common U-Boot functions bitrev16() and crc16(). So replace custom driver CRC-16 implementation by common U-Boot functions. Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
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Implementation in linux/crc16.h provides standard CRC-16 algorithm with polynomial x^16 + x^15 + x^2 + 1. Use it and remove duplicate ext4 CRC-16 specific code. Signed-off-by:
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This implementation provides standard CRC-16 algorithm with polynomial x^16 + x^15 + x^2 + 1. Signed-off-by:
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File fs/ubifs/crc16.h is standard linux's crc16.h include file. So move it from fs/ubifs to include/linux where are also other linux include files. Signed-off-by:
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U-Boot CRC-16 implementation uses polynomial x^16 + x^12 + x^5 + 1 which is not standard CRC-16 algorithm, but it is known as CRC-16-CCITT. Rename file crc16.c to crc16-ccitt.c to reduce confusion. Signed-off-by:
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On P2020 board is SPL malloc simple always failing with error and loops: SD boot... alloc space exhausted Bad trap at PC: f8f8b5f0, SR: 21200, vector=d00 NIP: 00000000 XER: 00000000 LR: 00000000 REGS: f8f8b5f0 TRAP: 20000000 DAR: 00000000 MSR: 00021200 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 GPR08: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 GPR24: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Call backtrace: Exception in kernel pc f8f8b5f0 signal 0 Inspection showed that gd->malloc_limit is zero. And it is because generally SPL_FRAMEWORK initialize SPL's gd->malloc_limit. But when SPL_FRAMEWORK is not enabled then in most cases nobody initialize gd->malloc_limit and so SPL malloc simple does not work. So disable SPL_SYS_MALLOC_SIMPLE by default when SPL_FRAMEWORK is not enabled. SPL_SYS_MALLOC_SIMPLE can be disabled only by setting SPL_SYS_MALLOC_F_LEN to zero. So do it. This change fixes SPL error "alloc space exhausted" on P2020 board. Signed-off-by: -
https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini authored
- mrvl_uart.sh: Remove script (Pali) - Fix Espressobin build for configs where ENV is not in SPI (Rogier) - mvebu: a37xx: Add support for reading OTP (Pali) - mvebu: uDPU: Ethernet fixes and misc DT and defconfig changes (Robert) - mvebu: Add support for reading LD0 and LD1 eFuse (Pali) - kwboot: Replace fstat()+st_size by lseek()+SEEK_END (Pali) - mvebu: turris_omnia: Enable CONFIG_CMD_FUSE (Pali) - arm: Add CONFIG_SPL_SYS_NO_VECTOR_TABLE used on 32bit MVEBU (Pali) - mvebu: a37xx: Add support for writing Security OTP values (Pali) - mvebu: turris: Misc enhancements and cleanups / fixes (Pali) - Sheevaplug : Use Marvell uclass mvgbe and PHY driver for Ethernet (Tony)
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Tom Rini authored
- For the environment, add a arch_env_get_location hook and make use of it on some NXP platforms (so that boards can override SoCs). - Remove some unused squashfs code from SPL - Resync am335x beaglebone related DTS files - Enable SPL_SEPARATE_BSS if SPL_BSS_START_ADDR is used
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Fix wrong environment.h and remove DECLARE_GLOBAL_DATA_PTR Fixes: 30e39ac7 (imx: imx7 Support for Manufacturing Protection) Signed-off-by:
Ye Li <ye.li@nxp.com> Reviewed-by:
Gaurav Jain <gaurav.jain@nxp.com>
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Update the Kconfig and Makefile to allow build for iMX8M and restrict the build only in u-boot. Signed-off-by:
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HW accelerated hash operations are giving incorrect hash output. so invalidate cache lines to avoid cache overwriting in DDR memory region. caam_hash() -moved address alignment check in the beginning of function. -added invalidate_dcache_range for pout buffer before running descriptor. Fixes: d7af2baa (crypto/fsl: Fix HW accelerated hash commands) Signed-off-by:
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The imx8mn_evk target have been converted to use binman. With the binman approach the ATF load address is described via devicetree, so remove the now unneeded instruction of exporting ATF_LOAD_ADDR. Signed-off-by: -
There is no reason for disabling I-cache and D-cache in SPL. Remove the unneeded CONFIG_SPL_SYS_ICACHE_OFF and CONFIG_SPL_SYS_DCACHE_OFF options. Signed-off-by: -
Enable DM_SERIAL for both U_Boot and the SPL. The uart4 and its pinmux are already marked with u-boot,dm-spl but we need to move the call to preloader_console_init() after spl_init() to avoid a board hang as dm can't be used until after spl_init(). Remove the manual config of the UART pinmux now that it is no longer needed. Signed-off-by:
Michael Trimarchi <michael@amarulasolutions.com> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by:
Ariel D'Alessandro <ariel.dalessandro@collabora.com>
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Add support for OF-LIST to common imx8mp-u-boot.dtsi so that it can be used with boards that have multiple DTB's. Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by:
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issue: blob decapsulation operation store the decrypted data in memory even if ICV check failed. fix: clear the blob data output memory. Fixes: c5de15cb (crypto/fsl: Add command for encapsulating/decapsulating blobs) Signed-off-by:Kshitiz Varshney <kshitiz.varshney@nxp.com> Tested-by:
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Marked related nodes as u-boot,dm-spl for serial driver model Enable CONFIG_DM_SERIAL Signed-off-by: -
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. move the preloader_console_init() call after spl_init() to avoid board hang Signed-off-by:
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