- Aug 11, 2020
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Lokesh Vutla authoredIn main control mmr there is no partition 4 and partition 6 is available only on J721e. Fix the same in ctrl_mmr_unlock function Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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Lokesh Vutla authored
Add an api soc_is_j721e(), and use it to enable certain functionality that is available only on j721e. This detection is needed when DT is not available. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: -
Lokesh Vutla authored
Starting J7200 SoC, ROM supports for loading sysfw directly from boot image. In such cases, SPL need not load sysfw from boot media, but need to receive boot notification message from sysfw. So separate out remoteproc calls for system controller from sysfw loader and just receive the boot notification if sysfw is already loaded. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
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Lokesh Vutla authored
mmr_unlock api is common for all k3 devices. Move it to a common location. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: -
If SPL_MULTI_DTB_FIT is not enabled, then CONFIG_SPL_OF_LIST is not defined And in turn tispl.bin ends up not embedding any DTB. Fixing it by using CONFIG_DEFAULT_DEVICE_TREE if SPL_OF_LIST is empty. Signed-off-by:
Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> -
The DT nodes on J721E SoCs currently use a node name "interconnect" for the various interconnects. This name is not following the DT schema, and should simply be "bus". Update the fdt fixup logic to use both the current and the expected corrected path names so that this logic won't be broken with newer kernels. Signed-off-by: -
Lokesh Vutla authored
Guard all eeprom probe with TI_I2C_BOARD_DETECT to avoid reading eeprom when eeprom is not available Reviewed-by:
Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: -
Lokesh Vutla authored
Current usage of eeprom apis produce a build failure when CONFIG_TI_I2C_BOARD_DETECT is not defined. Add stub function for these apis to avoid build failures. Reviewed-by:
Lokesh Vutla <lokeshvutla@ti.com> -
Because of space constraints, create a new USB defconfig for R5 to faciliate booting from USB mass storage devices Signed-off-by:Faiz Abbas <faiz_abbas@ti.com>
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Because of space constraints, create a new USB defconfig for R5 to faciliate booting in USB peripheral (DFU) bootmode Signed-off-by: -
Enable configs to facilitate booting from USB Mass Storage devices as well as USB peripheral boot Signed-off-by: -
Add offset and environment related configs used for booting from DFU. Signed-off-by: -
Add nodes for USB0 in SPL to enable USB host boot mode Signed-off-by: -
Add USB0 nodes and set them to host mode to support USB host and peripheral boot modes Signed-off-by: -
Add support for identifying USB host and device boot modes Signed-off-by: -
U-boot only supports either USB host or device mode for a node at a time in dts. To support both host and dfu bootmodes, set "peripheral" as the default dr_mode but fixup property to "host" if host bootmode is detected. This needs to happen before the dwc3 generic layer binds the usb device to a host or device driver. Therefore, add an fdtdec_setup_board() implementation to fixup the dt based on the boot mode. Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe in both the host and device cases. This is required for accessing the interface at USB 2.0 speeds. Signed-off-by: -
Gate mmc related system related configurations with DM_MMC to avoid build errors when MMC is not enabled Signed-off-by: -
Add support for loading system firmware from a USB mass storage device Signed-off-by: -
In order to be able to use things like file system drivers early on in SPL (before relocation) in a memory-constrained environment when DDR is not yet available we cannot use the simple malloc scheme which does not implement the freeing of previously allocated memory blocks. To address this issue go ahead and enable the use of the full malloc by manually initializing the required functionality inside board_init_f by creating a full malloc pool inside the pre-relocation malloc pool. Signed-off-by: -
usb_init() may be called multiple times for fetching multiple images from SPL. Skip reinitializing USB if its already been done Signed-off-by: -
Create a new API spl_usb_load() that takes the filename as a parameter instead of taking the default U-boot PAYLOAD_NAME Signed-off-by: -
The DT nodes on AM65x SoCs currently use a node name "interconnect" for the various interconnects. This name is not following the DT schema, and should simply be "bus". Update the fdt fixup logic to use both the current and the expected corrected path names so that this logic won't be broken with newer kernels. The logic also corrects the crypto node name as the DT node unit-addresses are all expected to be lower case. Signed-off-by: -
The hardcoded array size leads to array overflows with changes in speed modes enum in mmc core. Use MMC_MODES_END for otap_del_sel array declaration to fix this. Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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The various CBASS interconnect nodes on K3 J721E SoCs are defined using the node name "interconnect". This is not a valid node name as per the dt-schema. Fix these node names to use the standard name used for SoC interconnects, "bus". Signed-off-by: -
The various CBASS interconnect nodes on K3 AM65x SoCs are defined using the node name "interconnect". This is not a valid node name as per the dt-schema. Fix these node names to use the standard name used for SoC interconnects, "bus". Signed-off-by: -
This commit completes the migrations for DM_ETH and DM_USB. The board is now consistent with omap3_beagle and other remaining OMAP3 boards. Cc: Tom Rini <trini@konsulko.com> Cc: Adam Ford <aford173@gmail.com> Signed-off-by:Derald D. Woods <woods.technical@gmail.com>
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When switching on or off the ARM caches some care must be taken to ensure existing cache line allocations are not left in an inconsistent state. An example of this is when cache lines are considered non-shared by and L3 controller even though the lines are shared. To prevent these and other issues all cache lines should be cleared before enabling or disabling a coherent master's cache. ARM cores and many L3 controllers provide a way to efficiently clean out all cache lines to allow for this, unfortunately there is no such easy way to do this on current K3 MSMC based systems. We could explicitly clean out every valid external address tracked by MSMC (all of DRAM), or we could attempt to identify only the set of addresses accessed by a given boot stage and flush only those specifically. This patch attempts the latter. We start with cleaning the SPL load address. More addresses can be added here later as they are identified. Note that we perform a flush operation for both the flush and invalidate operations, this is not a typo. We do this to avoid the situation that some ARM cores will promote an invalidate to a clean+invalidate, but only emit the invalidation operation externally, leading to a loss of data. Signed-off-by:
Andrew F. Davis <afd@ti.com> Tested-by:
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Add DT entries for main domain watchdog0 and 1 instances on the J721e well as RTI1-based watchdog on the AM65x. RTI0 does not work for this purpose on the AM65x, so leave it out. On AM65x, we mark the power-domain as shared because RTI firmware such as https://github.com/siemens/k3-rti-wdt may request it as well in order to prevent accidental shutdown of the watchdog. Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com>
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This is based on the Linux kernel driver for the RTI watchdog. To actually reset the system on an AM65x, it requires firmware running on the R5 that accepts the NMI and issues the actual system reset via TISCI. Kind of an iTCO, except that this watchdog hardware has support for no-way-out, and only for that. On the J721E, reset works without extra firmware help when routing the RTI interrupt via the ESM. Signed-off-by:
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- Aug 10, 2020
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Tom Rini authored
Signed-off-by:Tom Rini <trini@konsulko.com>
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Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by: -
Use "cons.config.build_dir" instead of writing to the source directory (read-only). This will fix the test failures in Azure. Signed-off-by:Joao Marcos Costa <joaomarcos.costa@bootlin.com>
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- Aug 08, 2020
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Tom Rini authored
This converts the following to Kconfig: CONFIG_SYS_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_PART Note that with this conversion we now have consistent behavior with respect to ensuring that we have always selected the correct MMC device and hardware partition. Signed-off-by: -
At present with sunxi 64-bit, the Makefile builds u-boot-sunxi-with-spl.bin and then binman overwrites it with its own version. But the binman definition lacks some parts, in particular BL31. For now, work around this with a hack. Tested-by:
Andre Przywara <andre.przywara@arm.com> Tested-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by:
Simon Glass <sjg@chromium.org> Fixes: 42b18df8 ("x86: Makefile: Drop explicit targets built by binman")
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On some devices the environment variable serial# cannot be overwritten. Set the variable only if it is not set. For our unit test it is sufficient to test if any value for serial-number is set. Fixes: 8a5cdf60 ("test: efi_selftest: Do not force serial# setting") Signed-off-by:
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Tom Rini authored
- SquashFS support - Assorted bugfixes
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The hush parser not enabled for some boards, e.g. sipeed_maix_bitm_defconfig. With CONFIG_HUSH_PARSER=n a double quotation mark is not interpreted as the beginning of a string. Use a single quotation mark instead. Furthermore without the hush parser variables have to be referenced as ${varname}. Add the missing braces. Reported-by:Sean Anderson <seanga2@gmail.com> Fixes: 8b86c609 ("test/py: add test of basic shell functionality") Signed-off-by:
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Modify various test/py filesystem creation routines to support systems that don't implement the metadata_csum ext4 feature. Signed-off-by:Stephen Warren <swarren@nvidia.com>
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Add LED support for Cortina Access Presidio Engineering Board Signed-off-by:
Jway Lin <jway.lin@cortina-access.com> Signed-off-by:
Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Reviewed-by:
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Add Cortina Access LED controller support for CAxxxx SOCs Signed-off-by:
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