- Sep 12, 2022
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Running tests in parallel is much faster, e.g. 15 seconds to run the tests on sandbox (only), instead of 100 seconds (on a 16-core machine). Add a 'make pcheck' option to access this feature. Note that the tools/ tests still run each tool's tests once after the other, although within that, they do run in parallel. So for example, the buildman tests run in parallel, then the binman tests run in parallel. There would be a signiificant advantage to running them all in parallel together, but that would require a large amount of refactoring, e.g. with more use of pytest fixtures. Update the documentation to represent the current state. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This breaks using pytest to run the tests. Drop it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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At present when -n is used, all workers try to build U-Boot at once. Add a lock to ensure that only one of them builds, with the others using the build that is produced. The lock file is removed on startup. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This is a lot of code in a function that is too long. Split out the building code. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Tidy up this code a little. Also use '-k' consistently, since -m is more limited in what it can accept. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This assumes that the GPIO starts as 0 but it does not if test_gpio_input() ran first and test_gpio_exit_statuses() was skipped. This can happen when running tests in parallel. Fix it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Mark all the tests in this file as slow, since they take a while. Signed-off-by:
Simon Glass <sjg@chromium.org>
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When doing a quick check we don't need to run all the vboot tests. Just run the first one, which is enough to catch most problems. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This test seems to fail when run in parallel. Mark it single-threaded to avoid any problems. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This test seems to interfere with the other test in this file. Mark it single-threaded to avoid any problems. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Use a different temporary dir for each test, to allow them to run in parallel. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This test seems to rely on the other test in this file. Mark it single-threaded to avoid any problems. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Add a new 'singlethread' marker to allow tests to be skipped when running in parallel. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This test relies on the silent_linux env variable being set. Add this to the code so it can run without relying on other bootm tests having been run first. Signed-off-by:
Simon Glass <sjg@chromium.org>
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At present test_pinmux_status() assumes that test_pinmux_dev() has run beforehand. Drop this assumption so we can run the tests in parallel. Signed-off-by:
Simon Glass <sjg@chromium.org>
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- Sep 03, 2022
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Tom Rini authored
- DM RTC improvements that should help in CI, allow disabling LTO from the make line, add extension (cape, etc) support to distro bootcmd, add a pause command and re-enable ARM v4T support.
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- Sep 02, 2022
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At present the sandbox timer uses localtime() which can jump around twice a year when daylight-saving time changes. It would be tricky to make use of gmtime() since we still need to present the time in local time, as seems to be required by U-Boot's RTC interface. The problem can only happen once, so use a loop to detect it and try again. This should be sufficient to detect either a change in the 'second' value, or a daylight-saving change. We can assume that the latter also incorporates a 'second' change, so there is no need to loop more than twice. Signed-off-by:
Simon Glass <sjg@chromium.org>
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It seems that the time can change in between getting it and reading the offset. Check for this and try again if this happens. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Since resetting the RTC on sandbox causes it to read the base time from the system, we cannot rely on this being unchanged since it was last read. Allow for a one-second delay. Reviewed-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Fixes: u-boot/u-boot#4 Reported-by:
Bin Meng <bmeng.cn@gmail.com> Reported-by:
Tom Rini <trini@konsulko.com> Suggested-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by:
Simon Glass <sjg@chromium.org>
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Some tests can have race conditions which are hard to detect on a single one. Add a way to run tests more than once, to help with this. Each individual test is run the requested number of times before moving to the next test. If any runs failed, a message is shown. This is most useful when running a single test, since running all tests multiple times can take a while. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Use this (newish) macro since it is designed for the purpose of making sure things are non-NULL. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Check that sandbox builds and runs tests OK with LTO disabled. Signed-off-by:
Simon Glass <sjg@chromium.org>
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LTO (Link-Time Optimisation) is an very useful feature which can significantly reduce the size of U-Boot binaries. So far it has been made available for selected ARM boards and sandbox. However, incremental builds are much slower when LTO is used. For example, an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7 seconds with LTO enabled. Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be disabled during development if needed, for faster builds. Add some documentation about LTO while we are here. Signed-off-by:
Simon Glass <sjg@chromium.org>
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There is currently a problem that U-Boot can not work on ARMv4 because assembly imlementations of memcpy() and some other functions use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr" should be used instead). A working preprocessor-based solution to this problem is found in arch/arm/lib/relocate.S. Move it to the "ret" macro in arch/arm/include/asm/assembler.h and change all "bx lr" code to "ret lr" in functions that may run on ARMv4. Linux source code deals with this problem in the same manner. v1 -> v2: Comment update. Pointed out by Andre Przywara. Signed-off-by:
Sergei Antonov <saproj@gmail.com> CC: Samuel Holland <samuel@sholland.org> CC: Ye Li <ye.li@nxp.com> CC: Simon Glass <sjg@chromium.org> CC: Andre Przywara <andre.przywara@arm.com> CC: Marek Vasut <marex@denx.de> CC: Sean Anderson <sean.anderson@seco.com> CC: Tom Rini <trini@konsulko.com>
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This command is being introduced with the goal of allowing user-friendly "generic use case" U-Boot builds to pause until user input under some situations. The main use case would be when a boot failure happens, to pause until the user has had time to acknowledge the current state. Tested using: make && ./u-boot -v -T -c 'ut lib lib_test_hush_pause' Signed-off-by:
Samuel Dionne-Riel <samuel@dionne-riel.com> Cc: Simon Glass <sjg@chromium.org>
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Try to load required DTB overlays if the board supports extensions and CONFIG_CMD_EXTENSION is enabled. Signed-off-by:
Matwey V. Kornilov <matwey.kornilov@gmail.com>
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Tom Rini authored
- Assorted Kconfig migrations
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- Sep 01, 2022
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Enable d-cache early in SPL right after DRAM is started up. This reduces U-Boot proper load time by 650ms when loaded from SPI NOR. Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Philip Oberfichtner <pro@denx.de>
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Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the SPL to build cache-pl310.c. Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds. After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build. [1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable() Signed-off-by:
Philip Oberfichtner <pro@denx.de>
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This converts CONFIG_SYS_L2_PL310 to Kconfig. For omap2 and mvebu the 'select SYS_L2_PL310' locations were determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310. For mx6 I manually chose ARCH_MX6 as 'select' location. The correctness has been verified using $ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF 0 matches That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert the 'select' statement under ARCH_MX6. Signed-off-by:
Philip Oberfichtner <pro@denx.de>
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Tom Rini authored
This removes the following symbols: CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS CONFIG_SYS_I2C_LDI_ADDR CONFIG_SYS_I2C_DVI_ADDR CONFIG_SYS_I2C_DVI_BUS_NUM They are unused by any code in tree at this time. Signed-off-by:
Tom Rini <trini@konsulko.com>
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Tom Rini authored
This converts the following to Kconfig: CONFIG_SYS_I2C_EEPROM_CCID CONFIG_SYS_I2C_EEPROM_NXID CONFIG_SYS_EEPROM_BUS_NUM Signed-off-by:
Tom Rini <trini@konsulko.com>
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- Aug 26, 2022
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Tom Rini authored
- Assorted Arm, TI and Qualcomm platform updates
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We can check if the message was acknowledged in the common ti_sci_do_xfer() which lets us remove it from after each call to this function. This simplifies the code and reduces binary size. Signed-off-by:
Andrew Davis <afd@ti.com>
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The inline hint is not needed here, the compiler will do the right thing based on if we are compiling for speed or for code size. In this case the inline causes this function to be placed inside each callsite which is not the right thing to do for either speed nor size. There is no performance benefit to this due to the larger function size reducing cache locality, but there is a huge size penalty. Remove inline keyword. Signed-off-by:
Andrew Davis <afd@ti.com>
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We don't need to print the same message in every location, just print it in the function that fails and remove all the extra message printouts. Signed-off-by:
Andrew Davis <afd@ti.com>
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This ti_sci_do_xfer() function already prints out the reason for the failure, and the caller of each of these functions should also notify the user of the failed task. Remove this extra level of error message. Signed-off-by:
Andrew Davis <afd@ti.com>
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Currently for all Qcom SoCs/boards there are separate compatibles for GPIO and pinctrl. But this is inconsistent with official (upstream) Linux bindings which requires only a single compatible "qcom,<SoC name>-pinctrl" and there is no such compatible property as "qcom,tlmm-<SoC name>". So fix this inconsistency for Qcom SoCs in order to comply with upstream DT bindings. This is done via removing compatibles from "msm_gpio" driver and via binding to "msm_gpio" driver from pinctrl driver in case "gpio-controller" property is specified for pinctrl node. Suggested-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
Sumit Garg <sumit.garg@linaro.org>
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DT compatible is sufficient to make platform specific differentiation, so remove redundant CONFIG_SDM845 check. Signed-off-by:
Sumit Garg <sumit.garg@linaro.org> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
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Enable USB config options along with its dependencies like PHY, RESET, PMIC GPIO etc. config options. Signed-off-by:
Sumit Garg <sumit.garg@linaro.org>
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